diff options
| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-08 22:51:23 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-08 22:51:23 +0000 |
| commit | c2f87b7bb288fc9a5cfa3202533a744783705b9b (patch) | |
| tree | 61044090d0118fd535ef168c2640475aa5d79d16 /llvm/utils/TableGen/X86RecognizableInstr.cpp | |
| parent | 044cab33250a3707ae30ea69c5017e295f31a10e (diff) | |
| download | bcm5719-llvm-c2f87b7bb288fc9a5cfa3202533a744783705b9b.tar.gz bcm5719-llvm-c2f87b7bb288fc9a5cfa3202533a744783705b9b.zip | |
Reapply r105521, this time appending "LLU" to 64 bit
immediates to avoid breaking the build.
llvm-svn: 105652
Diffstat (limited to 'llvm/utils/TableGen/X86RecognizableInstr.cpp')
| -rw-r--r-- | llvm/utils/TableGen/X86RecognizableInstr.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index b7085ae6c7b..5fe2bfec1d4 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -212,6 +212,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix"); HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); + HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix"); HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); @@ -532,7 +533,12 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { "Unexpected number of operands for MRMSrcRegFrm"); HANDLE_OPERAND(roRegister) HANDLE_OPERAND(rmRegister) - HANDLE_OPTIONAL(immediate) + + if (HasVEX_4VPrefix) + // FIXME: encoding of registers in AVX is in 1's complement form. + HANDLE_OPTIONAL(rmRegister) + else + HANDLE_OPTIONAL(immediate) break; case X86Local::MRMSrcMem: // Operand 1 is a register operand in the Reg/Opcode field. |
