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author | Eli Friedman <eli.friedman@gmail.com> | 2011-07-16 02:41:28 +0000 |
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committer | Eli Friedman <eli.friedman@gmail.com> | 2011-07-16 02:41:28 +0000 |
commit | 0318036c4dd100b71ec1b59760c6c1f9710dc0b7 (patch) | |
tree | 9cefa3302e3bd4603b17c6fcd9a72f83197c25d6 /llvm/utils/TableGen/X86RecognizableInstr.cpp | |
parent | 0c5ef693a2b0fef31b43b079bb70e9abd4c3b652 (diff) | |
download | bcm5719-llvm-0318036c4dd100b71ec1b59760c6c1f9710dc0b7.tar.gz bcm5719-llvm-0318036c4dd100b71ec1b59760c6c1f9710dc0b7.zip |
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
llvm-svn: 135337
Diffstat (limited to 'llvm/utils/TableGen/X86RecognizableInstr.cpp')
-rw-r--r-- | llvm/utils/TableGen/X86RecognizableInstr.cpp | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index f7518a988cc..ea3bb700b27 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -229,6 +229,30 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, HasFROperands = hasFROperands(); HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L"); + // Check for 64-bit inst which does not require REX + Is64Bit = false; + // FIXME: Is there some better way to check for In64BitMode? + std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); + for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { + if (Predicates[i]->getName().find("64Bit") != Name.npos) { + Is64Bit = true; + break; + } + } + // FIXME: These instructions aren't marked as 64-bit in any way + Is64Bit |= Rec->getName() == "JMP64pcrel32" || + Rec->getName() == "MASKMOVDQU64" || + Rec->getName() == "POPFS64" || + Rec->getName() == "POPGS64" || + Rec->getName() == "PUSHFS64" || + Rec->getName() == "PUSHGS64" || + Rec->getName() == "REX64_PREFIX" || + Rec->getName().find("VMREAD64") != Name.npos || + Rec->getName().find("VMWRITE64") != Name.npos || + Rec->getName().find("MOV64") != Name.npos || + Rec->getName().find("PUSH64") != Name.npos || + Rec->getName().find("POP64") != Name.npos; + ShouldBeEmitted = true; } @@ -276,7 +300,7 @@ InstructionContext RecognizableInstr::insnContext() const { insnContext = IC_VEX_XS; else insnContext = IC_VEX; - } else if (Name.find("64") != Name.npos || HasREX_WPrefix) { + } else if (Is64Bit || HasREX_WPrefix) { if (HasREX_WPrefix && HasOpSizePrefix) insnContext = IC_64BIT_REXW_OPSIZE; else if (HasOpSizePrefix) |