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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-05 03:53:24 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-05 03:53:24 +0000 |
| commit | 594fa26317faa03e052b167d48365766310ebef3 (patch) | |
| tree | faeb70b0798dd935f6ee7af907996b4d5d7ccb6a /llvm/utils/TableGen/X86RecognizableInstr.cpp | |
| parent | c4f614870fcf923185cd1bfd7fa915b3cc9a541e (diff) | |
| download | bcm5719-llvm-594fa26317faa03e052b167d48365766310ebef3.tar.gz bcm5719-llvm-594fa26317faa03e052b167d48365766310ebef3.zip | |
Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.
llvm-svn: 105521
Diffstat (limited to 'llvm/utils/TableGen/X86RecognizableInstr.cpp')
| -rw-r--r-- | llvm/utils/TableGen/X86RecognizableInstr.cpp | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp index b7085ae6c7b..5fe2bfec1d4 100644 --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -212,6 +212,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix"); HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); + HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix"); HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); @@ -532,7 +533,12 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { "Unexpected number of operands for MRMSrcRegFrm"); HANDLE_OPERAND(roRegister) HANDLE_OPERAND(rmRegister) - HANDLE_OPTIONAL(immediate) + + if (HasVEX_4VPrefix) + // FIXME: encoding of registers in AVX is in 1's complement form. + HANDLE_OPTIONAL(rmRegister) + else + HANDLE_OPTIONAL(immediate) break; case X86Local::MRMSrcMem: // Operand 1 is a register operand in the Reg/Opcode field. |
