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* TableGen: Use enum names in composeSubRegIndices tableMatt Arsenault2019-10-271-1/+1
| | | | | I'm not sure why this is using the raw enum value. This makes reading the generated table comprehensible.
* Retire llvm::less/equal in favor of C++14 std::less<>/equal_to<>.Benjamin Kramer2019-08-221-2/+2
| | | | llvm-svn: 369674
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* Use the container form llvm::sort(C)Fangrui Song2018-10-311-1/+1
| | | | llvm-svn: 345682
* [MC] Remove PhysRegSize from MCRegisterClassBjorn Pettersson2018-08-091-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: The interface to get size and spill size of a register was moved from MCRegisterInfo to TargetRegisterInfo over a year ago. Afaik the old interface has bee around to give out-of-tree targets a chance to adapt to the new interface. One problem with the old MCRegisterClass::PhysRegSize was that it represented the size of a register as "size in bits" / 8. So a register had to be a multiple of eight bits wide for the size to be correct (and the byte size for the target needed to be eight bits). Reviewers: kparzysz, qcolombet Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D47199 llvm-svn: 339350
* [tablegen] Improve performance of -gen-register-info by replacing ↵Daniel Sanders2018-08-081-11/+51
| | | | | | | | | | | | | | | | | | | | | | | | barely-necessary std::map with a sorted vector Summary: This particular map is hardly ever queried and has a phased usage pattern (insert, iterate, query, insert, iterate) so it's a good candidate for a sorted vector and std::lower_bound. This significantly reduces the run time of runTargetDesc() in some circumstances. One llvm-tblgen invocation in my build improves the time spent in runTargetDesc() from 9.86s down to 0.80s (~92%) without changing the output. The same invocation also has 2GB less allocation churn. Reviewers: bogner, rtereshin, aditya_nandakumar, volkan Reviewed By: rtereshin Subscribers: mgrang, dexonsmith, llvm-commits Differential Revision: https://reviews.llvm.org/D50272 llvm-svn: 339208
* [TableGen] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | Summary: r327219 added wrappers to std::sort which randomly shuffle the container before sorting. This will help in uncovering non-determinism caused due to undefined sorting order of objects having the same key. To make use of that infrastructure we need to invoke llvm::sort instead of std::sort. Note: This patch is one of a series of patches to replace *all* std::sort to llvm::sort. Refer the comments section in D44363 for a list of all the required patches. Reviewers: stoklund, kparzysz, dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45144 llvm-svn: 329451
* Fix layering of MachineValueType.h by moving it from CodeGen to SupportDavid Blaikie2018-03-231-3/+3
| | | | | | | | | This is used by llvm tblgen as well as by LLVM Targets, so the only common place is Support for now. (maybe we need another target for these sorts of things - but for now I'm at least making them correct & we can make them better if/when people have strong feelings) llvm-svn: 328395
* [X86] Add phony registers for high halves of regs with low halvesKrzysztof Parzyszek2018-03-201-2/+2
| | | | | | | | | | | | | | | | | Registers E[A-D]X, E[SD]I, E[BS]P, and EIP have 16-bit subregisters that cover the low halves of these registers. This change adds artificial subregisters for the high halves in order to differentiate (in terms of register units) between the 32- and the low 16-bit registers. This patch contains parts that aim to preserve the calculated register pressure. This is in order to preserve the current codegen (minimize the impact of this patch). The approach of having artificial subregisters could be used to fix PR23423, but the pressure calculation would need to be changed. Differential Revision: https://reviews.llvm.org/D43353 llvm-svn: 328016
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
| | | | | | | | All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). llvm-svn: 318490
* [TableGen] : Simplify RegisterInfoEmitterJaved Absar2017-10-131-6/+4
| | | | llvm-svn: 315700
* Move "(void)variable" closer to the assertion that uses it, NFCKrzysztof Parzyszek2017-09-191-1/+1
| | | | llvm-svn: 313649
* Silence warning about unused variable in release buildKrzysztof Parzyszek2017-09-141-0/+1
| | | | llvm-svn: 313273
* TableGen support for parameterized register class informationKrzysztof Parzyszek2017-09-141-20/+64
| | | | | | | | | | | | | | | | | | | | | | | | | This replaces TableGen's type inference to operate on parameterized types instead of MVTs, and as a consequence, some interfaces have changed: - Uses of MVTs are replaced by ValueTypeByHwMode. - EEVT::TypeSet is replaced by TypeSetByHwMode. This affects the way that types and type sets are printed, and the tests relying on that have been updated. There are certain users of the inferred types outside of TableGen itself, namely FastISel and GlobalISel. For those users, the way that the types are accessed have changed. For typical scenarios, these replacements can be used: - TreePatternNode::getType(ResNo) -> getSimpleType(ResNo) - TreePatternNode::hasTypeSet(ResNo) -> hasConcreteType(ResNo) - TypeSet::isConcrete -> TypeSetByHwMode::isValueTypeByHwMode(false) For more information, please refer to the review page. Differential Revision: https://reviews.llvm.org/D31951 llvm-svn: 313271
* TableGen: Add -gen-register-info-debug-dumpMatthias Braun2017-08-281-4/+67
| | | | | | | | | | | | | | | | | | Adds a new --gen-register-info-debug-dump mode to tablegen that dumps various register related information: - List of register classes with super and subclasses - List of subregister indexes with lanemasks - List of registers with subregisters I will use this in an upcoming commit to create a test. It may also be useful for target developers wanting to get an overview of all the register related information, esp. the things inferred by tablegen and not directly visible in the .td file. Differential Revision: https://reviews.llvm.org/D36911 llvm-svn: 311913
* Break up long lines, NFCKrzysztof Parzyszek2017-06-281-2/+4
| | | | llvm-svn: 306585
* [TableGen] Adapt more places to getValueAsString now returning a StringRef ↵Craig Topper2017-05-311-4/+3
| | | | | | instead of a std::string. llvm-svn: 304347
* Move spill size and alignment info from MC to TargetRegisterInfoKrzysztof Parzyszek2017-03-241-7/+7
| | | | | | | | | | | | This is another step towards implementing register classes with parametrized register/spill sizes and value types. This is an updated version of r298652. The difference is that MCRegister- Class still contains register size, available as getPhysRegSize(). The old function getSize was retained as a temporary measure to avoid build breakage for out-of-tree targets. llvm-svn: 298739
* Revert r298652 on Quentin's requestKrzysztof Parzyszek2017-03-241-4/+4
| | | | llvm-svn: 298727
* Move spill size and alignment info from MC to TargetRegisterInfoKrzysztof Parzyszek2017-03-231-4/+4
| | | | | | | | | This is another step towards implementing register classes with parametrized register/spill sizes. Differential Revision: https://reviews.llvm.org/D31299 llvm-svn: 298652
* Implement LaneBitmask::any(), use it to replace !none(), NFCIKrzysztof Parzyszek2016-12-161-2/+2
| | | | llvm-svn: 289974
* Fix ubsan failures in lane mask shiftsKrzysztof Parzyszek2016-12-151-4/+8
| | | | llvm-svn: 289826
* Extract LaneBitmask into a separate typeKrzysztof Parzyszek2016-12-151-30/+30
| | | | | | | | | | | | Specifically avoid implicit conversions from/to integral types to avoid potential errors when changing the underlying type. For example, a typical initialization of a "full" mask was "LaneMask = ~0u", which would result in a value of 0x00000000FFFFFFFF if the type was extended to uint64_t. Differential Revision: https://reviews.llvm.org/D27454 llvm-svn: 289820
* TableGen: Use StringRef instead of const std::string& in return vals.Matthias Braun2016-12-041-1/+1
| | | | | | | This will allow to switch to a different string storage in an upcoming commit. llvm-svn: 288612
* [Sparc] Use target name instead of namespace as prefix for MCRegisterClasses ↵Jacob Baungard Hansen2016-11-211-1/+1
| | | | | | | | | | | | | | | | | | | array Summary: For Sparc the namespace (SP) is different from the target name (Sparc), which causes the name of the array in this declaration to differ from the name used in the definition. Patch by Daniel Cederman. Reviewers: jyknight Subscribers: llvm-commits, jyknight Differential Revision: https://reviews.llvm.org/D23650 llvm-svn: 287528
* [tablegen] Merge duplicate definitions of getMinimalTypeForRange. NFC.Daniel Sanders2016-11-191-16/+9
| | | | | | | | | | | | Summary: Depends on D25614 Reviewers: qcolombet Subscribers: qcolombet, beanz, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D25617 llvm-svn: 287438
* Avoid some copies by using const references.Benjamin Kramer2016-05-271-1/+1
| | | | | | | clang-tidy's performance-unnecessary-copy-initialization with some manual fixes. No functional changes intended. llvm-svn: 270988
* Fix Clang-tidy modernize-use-bool-literals in generated Target code; other ↵Eugene Zelenko2016-05-171-26/+43
| | | | | | | | | | | | minor fixes; other minor fixes. Make generated code more readable. Fix some Include What You Use warnings. Differential revision: http://reviews.llvm.org/D20317 llvm-svn: 269783
* TableGen: Produce CoveredBySubRegs summary for register classesMatthias Braun2016-04-281-1/+3
| | | | | | This will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267850
* TargetRegisterInfo: Introduce reverseComposeSubRegIndexLaneMask()Matthias Braun2016-04-281-12/+29
| | | | | | | | | This function performs the reverse computation of composeSubRegIndexLaneMask(). It will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267849
* Remove extra 'nullptr' entry from an array in tablegen register info file. ↵Craig Topper2015-09-221-1/+1
| | | | | | It should never have been accessed. llvm-svn: 248246
* Fix formatting of a tablegen register info file by putting a line break in a ↵Craig Topper2015-09-221-3/+2
| | | | | | better place. llvm-svn: 248245
* Use makeArrayRef and None to simplify some code in a tablegen register info ↵Craig Topper2015-09-221-12/+18
| | | | | | | | | | file. Additionally const correct a couple static array. Previously the code added an extra nullptr entry to a static array and then created an ArrayRef with a size one less than the static array. If there were no other entries the array would just contain the nullptr and the ArrayRef would be crated with size 0. Instead, put the right number of entries in the array and explicitly emit 'None' if the size would be 0. This allows the static array constructor of makeArrayRef to be used. llvm-svn: 248244
* Targets: commonize some stack realignment codeJF Bastien2015-07-201-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 llvm-svn: 242727
* Target RegisterInfo: devirtualize TargetFrameLoweringJF Bastien2015-07-101-0/+12
| | | | | | | | | | | | | Summary: The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can. This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here. Subscribers: sunfish, ted, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11093 llvm-svn: 241921
* MIR Serialization: Serialize the register mask machine operands.Alex Lorenz2015-06-291-0/+22
| | | | | | | | | | | | | | | | | This commit implements serialization of the register mask machine operands. This commit serializes only the call preserved register masks that are defined by a target, it doesn't serialize arbitrary register masks. This commit also extends the TargetRegisterInfo class and TableGen so that the users of TRI can get the list of all the call preserved register masks and their names. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10673 llvm-svn: 240966
* TableGen: Generate more const goodnessMatthias Braun2015-04-011-2/+2
| | | | llvm-svn: 233857
* RegAllocGreedy: Allow target to specify register class ordering.Matthias Braun2015-03-311-0/+1
| | | | | | | | | | Specify an allocation order with a register class. This is used by register allocators with a greedy heuristic. This is usefull as it is sometimes beneficial to color more constrained classes first. Differential Revision: http://reviews.llvm.org/D8626 llvm-svn: 233743
* Do not track subregister liveness when it brings no benefitsMatthias Braun2015-03-191-1/+3
| | | | | | | | | | | Some subregisters are only to indicate different access sizes, while not providing any way to actually divide the register up into multiple disjunct parts. Avoid tracking subregister liveness in these cases as it is not beneficial. Differential Revision: http://reviews.llvm.org/D8429 llvm-svn: 232695
* Have getRegPressureSetLimit take a MachineFunction so that aEric Christopher2015-03-111-2/+3
| | | | | | we can inspect the subtarget and function when computing values. llvm-svn: 231951
* TblGen: Remove copy of SmallVector::operator==. NFC intended.Benjamin Kramer2015-03-021-10/+1
| | | | llvm-svn: 230964
* Switch a std::map to a DenseMap in CodeGenRegisters.Owen Anderson2015-02-271-7/+9
| | | | | | | | The keys of the map are unique by pointer address, so there's no need to use the llvm::less comparator. This allows us to use DenseMap instead, which reduces tblgen time by 20% on my stress test. llvm-svn: 230769
* STLExtras: Provide less/equal functors with templated function call ↵David Blaikie2015-02-021-2/+2
| | | | | | | | | | | | | | | | operators, plus a deref'ing functor template utility Similar to the C++14 void specializations of these templates, useful as a stop-gap until LLVM switches to '14. Example use-cases in tblgen because I saw some functors that looked like they could be simplified/refactored. Reviewers: dexonsmith Differential Revision: http://reviews.llvm.org/D7324 llvm-svn: 227828
* Replace another std::set in the core of CodeGenRegister, this time with ↵Owen Anderson2015-01-311-1/+1
| | | | | | | | sorted arrays. The hot path through this region of code does lots of batch inserts into sets. By storing them as sorted arrays, we can defer the sorting to the end of the batch, which is dramatically more efficient. This reduces tblgen runtime by 25% on my worst-case target. llvm-svn: 227682
* Change more of the guts of CodeGenRegister's RegUnit tracking to be based on ↵Owen Anderson2015-01-311-8/+8
| | | | | | | | bit vectors. This is a continuation of my prior work to move some of the inner workings for CodeGenRegister to use bit vectors when computing about register units. This is highly beneficial to TableGen runtime on targets with large, dense register files. This patch represents a ~40% runtime reduction over and above my earlier improvement on a stress test of this case. llvm-svn: 227678
* Tablegen'erate lanemasks for register units.Matthias Braun2014-12-101-6/+35
| | | | | | Now we can relate lanemasks in a virtual register to register units. llvm-svn: 223889
* Add function that translates subregister lane masks to other subregs.Matthias Braun2014-12-101-1/+96
| | | | | | | This works like the composeSubRegisterIndices() function but transforms a subregister lane mask instead of a subregister index. llvm-svn: 223874
* Let tablegen compute maximum lanemask for regs/regclasses.Matthias Braun2014-12-101-1/+2
| | | | | | | | Let tablegen compute the combination of subregister lanemasks for all subregisters in a register/register class. This is preparation for further work subregister allocation llvm-svn: 223873
* Simplify ownership of RegClasses by using list<CodeGenRegisterClass> instead ↵David Blaikie2014-12-031-30/+19
| | | | | | | | | | of vector<CodeGenRegisterClass*> This complicates a few algorithms due to not having random access, but not by a huge degree I don't think (open to debate/design discussion/etc). llvm-svn: 223261
* Range-for some stuff related to RegClasses, and comment cases where ↵David Blaikie2014-12-031-47/+43
| | | | | | range-for isn't suitable. llvm-svn: 223260
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