summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff options
context:
space:
mode:
authorMatthias Braun <matze@braunis.de>2016-04-28 03:07:11 +0000
committerMatthias Braun <matze@braunis.de>2016-04-28 03:07:11 +0000
commit39d1fad55484af74f9132bb454fd0b7dab08a53b (patch)
tree7bb1af10eecf84f775c6963bed0135cf06b0fe4b /llvm/utils/TableGen/RegisterInfoEmitter.cpp
parentcd69bcf6d52abb4deeb698e274b3be1a7d490d9c (diff)
downloadbcm5719-llvm-39d1fad55484af74f9132bb454fd0b7dab08a53b.tar.gz
bcm5719-llvm-39d1fad55484af74f9132bb454fd0b7dab08a53b.zip
TableGen: Produce CoveredBySubRegs summary for register classes
This will be used in the upcoming "DetectDeadLanes" pass. llvm-svn: 267850
Diffstat (limited to 'llvm/utils/TableGen/RegisterInfoEmitter.cpp')
-rw-r--r--llvm/utils/TableGen/RegisterInfoEmitter.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index 4ec3e7de0f7..3316da6185c 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1311,7 +1311,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
<< format("0x%08x,\n ", RC.LaneMask)
<< (unsigned)RC.AllocationPriority << ",\n "
<< (RC.HasDisjunctSubRegs?"true":"false")
- << ", /* HasDisjunctSubRegs */\n ";
+ << ", /* HasDisjunctSubRegs */\n "
+ << (RC.CoveredBySubRegs?"true":"false")
+ << ", /* CoveredBySubRegs */\n ";
if (RC.getSuperClasses().empty())
OS << "NullRegClasses,\n ";
else
OpenPOWER on IntegriCloud