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path: root/llvm/utils/TableGen/CodeGenSchedule.h
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* Revert "Revert "[misched] Extend scheduler to handle unsupported features""Simon Dardis2016-06-241-0/+8
| | | | | | | | This reverts commit r273565. This was an over-eager revert. llvm-svn: 273658
* Revert "[misched] Extend scheduler to handle unsupported features"Simon Dardis2016-06-231-8/+0
| | | | | | | | This reverts commit r273551. Patch contained a wrong check for isUnsupported. llvm-svn: 273565
* [misched] Extend scheduler to handle unsupported featuresSimon Dardis2016-06-231-0/+8
| | | | | | | | | | | | | | | | | | | | | | | Currently isComplete = 1 requires that every instruction must be described, declared unsupported or marked as having no scheduling information for a processor. For some backends such as MIPS, this requirement entails long regex lists of instructions that are unsupported. This patch teaches Tablegen to skip over instructions that are associated with unsupported feature when checking if the scheduling model is complete. Patch by: Daniel Sanders Contributions by: Simon Dardis Reviewers: MatzeB Differential Reviewer: http://reviews.llvm.org/D20522 llvm-svn: 273551
* TableGen/CodeGenSchedule: Move some getAllDerivedDefinitions() calls out of ↵Matthias Braun2016-06-211-0/+3
| | | | | | | | | inner loops This cuts the runtime of the two slowest tblgen invocations in aarch64 in half for me... llvm-svn: 273235
* TableGen: Check scheduling models for completenessMatthias Braun2016-03-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | TableGen checks at compiletime that for scheduling models with "CompleteModel = 1" one of the following holds: - Is marked with the hasNoSchedulingInfo flag - The instruction is a subclass of Sched - There are InstRW definitions in the scheduling model Typical steps necessary to complete a model: - Ensure all pseudo instructions that are expanded before machine scheduling (usually everything handled with EmitYYY() functions in XXXTargetLowering). - If a CPU does not support some instructions mark the corresponding resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }". - Add missing scheduling information. Differential Revision: http://reviews.llvm.org/D17747 llvm-svn: 262384
* [TableGen] Use range-based for loops. NFCCraig Topper2016-02-131-0/+2
| | | | llvm-svn: 260809
* Use make_range to reduce mentions of iterator type. NFCCraig Topper2015-12-061-6/+4
| | | | llvm-svn: 254872
* [TblGen] ArrayRefize CodeGenSchedule. No functionality change intended.Benjamin Kramer2015-10-241-19/+20
| | | | llvm-svn: 251187
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* Move SetTheory from utils/TableGen into lib/TableGen so Clang can use it.James Molloy2014-06-171-1/+1
| | | | llvm-svn: 211100
* iterator access to scheduling classesJim Grosbach2014-04-181-0/+22
| | | | llvm-svn: 206552
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check ↵Craig Topper2014-04-161-3/+3
| | | | | | instead of comparing to nullptr. llvm-svn: 206356
* Fix known typosAlp Toker2014-01-241-2/+2
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* Support BufferSize on ProcResGroup for unified MOp schedulers.Andrew Trick2013-06-151-1/+4
| | | | | | And add Sandybridge/Haswell resource buffers. llvm-svn: 184034
* Machine model: verify well-formed processor resource groups.Andrew Trick2013-04-231-0/+3
| | | | llvm-svn: 180161
* Machine model. Allow mixed itinerary classes and SchedRW lists.Andrew Trick2013-03-161-39/+28
| | | | | | | | | | | | | We always supported a mixture of the old itinerary model and new per-operand model, but it required a level of indirection to map itinerary classes to SchedRW lists. This was done for ARM A9. Now we want to define x86 SchedRW lists, with the goal of removing its itinerary classes, but still support the itineraries in the mean time. When I original developed the model, Atom did not have itineraries, so there was no reason to expect this requirement. llvm-svn: 177226
* Fix an uninitialized member variable, found by -fsanitize=bool.Richard Smith2012-12-201-7/+8
| | | | llvm-svn: 170627
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-2/+2
| | | | | | | I've tried to find main moudle headers where possible, but the TableGen stuff may warrant someone else looking at it. llvm-svn: 169251
* TableGen subtarget emitter cleanup.Andrew Trick2012-10-101-0/+3
| | | | | | Consistently evaluate Aliases and Sequences recursively. llvm-svn: 165604
* Added instregex support to TableGen subtarget emitter.Andrew Trick2012-10-031-0/+4
| | | | | | | | This allows the processor-specific machine model to override selected base opcodes without any fanciness. e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>. llvm-svn: 165180
* TableGen subtarget emitter, nearly first class support for SchedAlias.Andrew Trick2012-10-031-10/+16
| | | | | | | | | A processor can now arbitrarily alias one SchedWrite onto another. Only the SchedAlias definition need be within the processor model. The aliased SchedWrite may be a SchedVariant, WriteSequence, or transitively refer to another alias. llvm-svn: 165179
* Machine Model (-schedmodel only). Added SchedAliases.Andrew Trick2012-09-221-8/+23
| | | | | | | Allow subtargets to tie SchedReadWrite types to processor specific sequences or variants. llvm-svn: 164451
* SchedMachineModel: compress the CPU's WriteLatencyTable.Andrew Trick2012-09-191-0/+3
| | | | llvm-svn: 164199
* comment typoAndrew Trick2012-09-181-1/+1
| | | | llvm-svn: 164097
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-181-9/+0
| | | | llvm-svn: 164096
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-1/+10
| | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
* comment typoAndrew Trick2012-09-171-1/+1
| | | | llvm-svn: 164064
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-171-9/+0
| | | | llvm-svn: 164063
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-151-0/+29
| | | | | | Collect processor resources from the subtarget defs. llvm-svn: 163953
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-151-0/+17
| | | | | | Infer SchedClasses from variants defined by the target or subtarget. llvm-svn: 163952
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-151-56/+228
| | | | | | Collect SchedClasses and SchedRW types from the subtarget defs. llvm-svn: 163951
* I'm introducing a new machine model to simultaneously allow simpleAndrew Trick2012-07-071-0/+172
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
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