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| author | Andrew Trick <atrick@apple.com> | 2012-10-03 23:06:32 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-10-03 23:06:32 +0000 |
| commit | 9e1deb69b9defa45679f24518a028c66fc8c9577 (patch) | |
| tree | 3b76b96a4d10edc7675a9b2d0a60b7c08802245c /llvm/utils/TableGen/CodeGenSchedule.h | |
| parent | da984b1aa9c40cde1f59f53b96589632e5742727 (diff) | |
| download | bcm5719-llvm-9e1deb69b9defa45679f24518a028c66fc8c9577.tar.gz bcm5719-llvm-9e1deb69b9defa45679f24518a028c66fc8c9577.zip | |
Added instregex support to TableGen subtarget emitter.
This allows the processor-specific machine model to override selected
base opcodes without any fanciness.
e.g. InstRW<[CoreXWriteVANDP], (instregex "VANDP")>.
llvm-svn: 165180
Diffstat (limited to 'llvm/utils/TableGen/CodeGenSchedule.h')
| -rw-r--r-- | llvm/utils/TableGen/CodeGenSchedule.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/CodeGenSchedule.h b/llvm/utils/TableGen/CodeGenSchedule.h index 211c05c8c64..cc3a10223b3 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.h +++ b/llvm/utils/TableGen/CodeGenSchedule.h @@ -15,6 +15,7 @@ #ifndef CODEGEN_SCHEDULE_H #define CODEGEN_SCHEDULE_H +#include "SetTheory.h" #include "llvm/TableGen/Record.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/ADT/DenseMap.h" @@ -208,6 +209,9 @@ class CodeGenSchedModels { RecordKeeper &Records; const CodeGenTarget &Target; + // Map dag expressions to Instruction lists. + SetTheory Sets; + // List of unique processor models. std::vector<CodeGenProcModel> ProcModels; |
