diff options
author | Richard Smith <richard-llvm@metafoo.co.uk> | 2012-12-20 01:05:39 +0000 |
---|---|---|
committer | Richard Smith <richard-llvm@metafoo.co.uk> | 2012-12-20 01:05:39 +0000 |
commit | a7bb16ad86189c16f89ac186147ba8ac945df2b3 (patch) | |
tree | fd8a644cdf25ffabef91060a1f15ca0f1db0e026 /llvm/utils/TableGen/CodeGenSchedule.h | |
parent | 28408a20c9d792866d21980789147207b945f7d8 (diff) | |
download | bcm5719-llvm-a7bb16ad86189c16f89ac186147ba8ac945df2b3.tar.gz bcm5719-llvm-a7bb16ad86189c16f89ac186147ba8ac945df2b3.zip |
Fix an uninitialized member variable, found by -fsanitize=bool.
llvm-svn: 170627
Diffstat (limited to 'llvm/utils/TableGen/CodeGenSchedule.h')
-rw-r--r-- | llvm/utils/TableGen/CodeGenSchedule.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/llvm/utils/TableGen/CodeGenSchedule.h b/llvm/utils/TableGen/CodeGenSchedule.h index dc927e68ff9..78f115ecd8b 100644 --- a/llvm/utils/TableGen/CodeGenSchedule.h +++ b/llvm/utils/TableGen/CodeGenSchedule.h @@ -55,10 +55,11 @@ struct CodeGenSchedRW { IdxVec Sequence; RecVec Aliases; - CodeGenSchedRW(): Index(0), TheDef(0), IsAlias(false), HasVariants(false), - IsVariadic(false), IsSequence(false) {} - CodeGenSchedRW(unsigned Idx, Record *Def): Index(Idx), TheDef(Def), - IsAlias(false), IsVariadic(false) { + CodeGenSchedRW() + : Index(0), TheDef(0), IsRead(false), IsAlias(false), + HasVariants(false), IsVariadic(false), IsSequence(false) {} + CodeGenSchedRW(unsigned Idx, Record *Def) + : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { Name = Def->getName(); IsRead = Def->isSubClassOf("SchedRead"); HasVariants = Def->isSubClassOf("SchedVariant"); @@ -72,9 +73,9 @@ struct CodeGenSchedRW { } CodeGenSchedRW(unsigned Idx, bool Read, const IdxVec &Seq, - const std::string &Name): - Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false), - HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) { + const std::string &Name) + : Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false), + HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) { assert(Sequence.size() > 1 && "implied sequence needs >1 RWs"); } |