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path: root/llvm/utils/TableGen/CodeGenSchedule.h
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* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [llvm-mca][MC] Add the ability to declare which processor resources model loa...Andrea Di Biagio2018-11-291-2/+9
* [MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.Clement Courbet2018-10-251-11/+1
* [tblgen][llvm-mca] Add the ability to describe move elimination candidates vi...Andrea Di Biagio2018-10-121-4/+11
* [llvm-exegesis] Add support for measuring NumMicroOps.Clement Courbet2018-09-261-1/+3
* Attempt to unbreak buidlbot lld-x86_64-darwin13 after r342555.Andrea Di Biagio2018-09-191-1/+1
* [TableGen][SubtargetEmitter] Add the ability for processor models to describe...Andrea Di Biagio2018-09-191-0/+141
* Test commit: remove trailing whitespaceJosh Stone2018-09-111-1/+1
* [Tablegen][MCInstPredicate] Removed redundant template argument from class TI...Andrea Di Biagio2018-08-141-0/+2
* Revert r338365: [X86] Improved sched models for X86 BT*rr instructions.Simon Pilgrim2018-07-311-2/+0
* [X86] Improved sched models for X86 BT*rr instructions.Andrew V. Tischenko2018-07-311-0/+2
* [Tablegen] Simplify code in CodeGenSchedule. NFCIAndrea Di Biagio2018-04-261-5/+2
* [MC][TableGen] Add optional libpfm counter names for ProcResUnits.Clement Courbet2018-04-101-1/+9
* [MC][Tablegen] Allow models to describe the retire control unit for llvm-mca. Andrea Di Biagio2018-04-051-2/+10
* [MC][Tablegen] Allow the definition of processor register files in the schedu...Andrea Di Biagio2018-04-031-0/+42
* [TableGen] Add a non-default constructor to CodeGenSchedClass and use it via ...Craig Topper2018-03-221-3/+4
* [SchedModel] Use CodeGenSchedClass::isKeyEqual instead of duplicating code. N...Simon Pilgrim2018-03-211-1/+2
* [TableGen] Remove a defaulted function argument that is never called with ano...Craig Topper2018-03-211-1/+1
* [TableGen] Move a function from llvm namespace and make it a static function....Craig Topper2018-03-211-3/+0
* [TableGen][NFC]Remove dead variable.Clement Courbet2018-01-261-1/+0
* [TableGen] Improve error reportingEvandro Menezes2017-11-211-3/+4
* [MiSched|TableGen] : Tidy up and modernise. NFC.Javed Absar2017-09-131-10/+10
* Revert "Revert "[misched] Extend scheduler to handle unsupported features""Simon Dardis2016-06-241-0/+8
* Revert "[misched] Extend scheduler to handle unsupported features"Simon Dardis2016-06-231-8/+0
* [misched] Extend scheduler to handle unsupported featuresSimon Dardis2016-06-231-0/+8
* TableGen/CodeGenSchedule: Move some getAllDerivedDefinitions() calls out of i...Matthias Braun2016-06-211-0/+3
* TableGen: Check scheduling models for completenessMatthias Braun2016-03-011-0/+2
* [TableGen] Use range-based for loops. NFCCraig Topper2016-02-131-0/+2
* Use make_range to reduce mentions of iterator type. NFCCraig Topper2015-12-061-6/+4
* [TblGen] ArrayRefize CodeGenSchedule. No functionality change intended.Benjamin Kramer2015-10-241-19/+20
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
* Move SetTheory from utils/TableGen into lib/TableGen so Clang can use it.James Molloy2014-06-171-1/+1
* iterator access to scheduling classesJim Grosbach2014-04-181-0/+22
* [C++11] More 'nullptr' conversion. In some cases just using a boolean check i...Craig Topper2014-04-161-3/+3
* Fix known typosAlp Toker2014-01-241-2/+2
* Support BufferSize on ProcResGroup for unified MOp schedulers.Andrew Trick2013-06-151-1/+4
* Machine model: verify well-formed processor resource groups.Andrew Trick2013-04-231-0/+3
* Machine model. Allow mixed itinerary classes and SchedRW lists.Andrew Trick2013-03-161-39/+28
* Fix an uninitialized member variable, found by -fsanitize=bool.Richard Smith2012-12-201-7/+8
* Sort the #include lines for utils/...Chandler Carruth2012-12-041-2/+2
* TableGen subtarget emitter cleanup.Andrew Trick2012-10-101-0/+3
* Added instregex support to TableGen subtarget emitter.Andrew Trick2012-10-031-0/+4
* TableGen subtarget emitter, nearly first class support for SchedAlias.Andrew Trick2012-10-031-10/+16
* Machine Model (-schedmodel only). Added SchedAliases.Andrew Trick2012-09-221-8/+23
* SchedMachineModel: compress the CPU's WriteLatencyTable.Andrew Trick2012-09-191-0/+3
* comment typoAndrew Trick2012-09-181-1/+1
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-181-9/+0
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-1/+10
* comment typoAndrew Trick2012-09-171-1/+1
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-171-9/+0
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