summaryrefslogtreecommitdiffstats
path: root/llvm/utils/TableGen/CodeGenRegisters.h
Commit message (Collapse)AuthorAgeFilesLines
...
* Precompute lists of explicit sub-registers and indices.Jakob Stoklund Olesen2012-05-101-0/+9
| | | | | | | | The .td files specify a tree of sub-registers. Store that tree as ExplicitSubRegs lists in CodeGenRegister instead of extracting it from the Record when needed. llvm-svn: 156555
* Compute a backwards SubReg -> SubRegIndex map for each register.Jakob Stoklund Olesen2012-05-091-0/+7
| | | | | | | | | | | | | | | | This mapping is for internal use by TableGen. It will not be exposed in the generated files. Unfortunately, the mapping is not completely well-defined. The X86 xmm registers appear with multiple sub-register indices in the ymm registers. This is because of the odd idempotent sub_sd and sub_ss sub-register indices. I hope to be able to eliminate them entirely, so we can require the sub-registers to form a tree. For now, just place the canonical sub_xmm index in the mapping, and ignore the idempotents. llvm-svn: 156519
* Rename getSubRegs() to computeSubRegs().Jakob Stoklund Olesen2012-05-091-2/+2
| | | | | | That's what it does. llvm-svn: 156518
* Remove TargetRegisterClass::SuperRegClasses.Jakob Stoklund Olesen2012-05-041-2/+0
| | | | | | | | This manually enumerated list of super-register classes has been superceeded by the automatically computed super-register class masks available through SuperRegClassIterator. llvm-svn: 156151
* TableGen's regpressure: emit per-registerclass weight limits.Andrew Trick2012-04-111-0/+12
| | | | llvm-svn: 154518
* Added register unit sets to the target description.Andrew Trick2012-04-101-0/+46
| | | | | | | | | | This is a new algorithm that finds sets of register units that can be used to model registers pressure. This handles arbitrary, overlapping register classes. Each register class is associated with a (small) list of pressure sets. These are the dimensions of pressure affected by the register class's liveness. llvm-svn: 154374
* Added register unit weights to the target description.Andrew Trick2012-04-101-2/+46
| | | | | | | | | | | | This is a new algorithm that associates registers with weighted register units to accuretely model their effect on register pressure. This handles registers with multiple overlapping subregisters. It is possible, but almost inconceivable that the algorithm fails to find an exact solution for a target description. If an exact solution cannot be found, an inexact, but reasonable solution will be chosen. llvm-svn: 154373
* Fix header commentAndrew Trick2012-04-101-2/+2
| | | | llvm-svn: 154372
* Introduce Register Units: Give each leaf register a number.Andrew Trick2012-03-311-0/+11
| | | | | | | | First small step toward modeling multi-register multi-pressure. In the future, register units can also be used to model liveness and aliasing. llvm-svn: 153794
* Add more constness to CodeGenRegisters.Jakob Stoklund Olesen2012-03-291-2/+2
| | | | llvm-svn: 153667
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-051-2/+2
| | | | llvm-svn: 149814
* Specify SubRegIndex components on the index itself.Jakob Stoklund Olesen2012-02-011-0/+3
| | | | | | | | | | | | | | | | | It is simpler to define a composite index directly: def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>; def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>; Than specifying the composite indices on each register: CompositeIndices = [(ssub_2 dsub_1, ssub_0), (ssub_3 dsub_1, ssub_1)] in ... This also makes it clear that SubRegIndex composition is supposed to be unique. llvm-svn: 149556
* Move the composite map into CodeGenSubRegIndex.Jakob Stoklund Olesen2012-01-311-8/+29
| | | | | | Each SubRegIndex keeps track of how it composes. llvm-svn: 149423
* Add a TableGen CodeGenSubRegIndex class.Jakob Stoklund Olesen2012-01-311-14/+49
| | | | | | | | | This class is used to represent SubRegIndex instances instead of the raw Record pointers that were used before. No functional change intended. llvm-svn: 149418
* Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen2012-01-181-0/+1
| | | | | | | | | | | | | | | | When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. llvm-svn: 148363
* Add TableGen support for callee saved registers.Jakob Stoklund Olesen2012-01-171-0/+9
| | | | | | | | | Targets can now add CalleeSavedRegs defs to their *CallingConv.td file. TableGen will use this to create a *_SaveList array suitable for returning from getCalleeSavedRegs() as well as a *_RegMask bit mask suitable for returning from getCallPreservedMask(). llvm-svn: 148346
* Emit a getMatchingSuperRegClass() implementation for every target.Jakob Stoklund Olesen2011-12-191-1/+17
| | | | | | | | | Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. llvm-svn: 146873
* Synthesize register classes for TRI::getMatchingSuperRegClass().Jakob Stoklund Olesen2011-12-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Teach TableGen to create the missing register classes needed for getMatchingSuperRegClass() to return maximal results. The function is still not auto-generated, so it still returns inexact results. This produces these new register classes: ARM: QQPR_with_dsub_0_in_DPR_8 QQQQPR_with_dsub_0_in_DPR_8 X86: GR64_with_sub_32bit_in_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP GR64_with_sub_16bit_in_GR16_NOREX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX GR64_with_sub_32bit_in_GR32_TC GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC GR64_with_sub_32bit_in_GR32_AD GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX The other targets in the tree are not weird enough to be affected. llvm-svn: 146872
* Extract a method. No functional change.Jakob Stoklund Olesen2011-12-161-0/+1
| | | | llvm-svn: 146713
* Synthesize missing register class intersections.Jakob Stoklund Olesen2011-12-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function TRI::getCommonSubClass(A, B) returns the largest common sub-class of the register classes A and B. This patch teaches TableGen to synthesize sub-classes such that the answer is always maximal. In other words, every register that is in both A and B will also be present in getCommonSubClass(A, B). This introduces these synthetic register classes: ARM: GPRnopc_and_hGPR GPRnopc_and_hGPR hGPR_and_rGPR GPRnopc_and_hGPR GPRnopc_and_hGPR hGPR_and_rGPR tGPR_and_tcGPR hGPR_and_tcGPR X86: GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR64_NOSP_and_GR64_TC GR64_NOSP_and_GR64_TC GR64_NOREX_and_GR64_TC GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR64_NOSP_and_GR64_TC GR64_NOREX_and_GR64_TC GR64_NOREX_NOSP_and_GR64_TC GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR32_ABCD_and_GR32_NOAX GR32_NOAX_and_GR32_NOSP GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR32_ABCD_and_GR32_NOAX GR32_NOAX_and_GR32_TC GR32_NOAX_and_GR32_NOSP GR64_NOSP_and_GR64_TC GR32_NOAX_and_GR32_NOREX GR32_NOAX_and_GR32_NOREX_NOSP GR64_NOREX_and_GR64_TC GR64_NOREX_NOSP_and_GR64_TC GR32_ABCD_and_GR32_NOAX GR64_ABCD_and_GR64_TC GR32_NOAX_and_GR32_TC GR32_AD_and_GR32_NOAX Other targets are unaffected. llvm-svn: 146657
* Extract a method.Jakob Stoklund Olesen2011-12-121-0/+5
| | | | llvm-svn: 146374
* Remove extra semicolon.Eli Friedman2011-10-111-1/+1
| | | | llvm-svn: 141699
* Add TRI::getSubClassWithSubReg(RC, Idx) function.Jakob Stoklund Olesen2011-10-051-0/+13
| | | | | | | | | | | | | | | | This function is used to constrain a register class to a sub-class that supports the given sub-register index. For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD. The function will be used to compute register classes when emitting INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation of sub-register operations. The version provided by TableGen is usually adequate, but targets can override. llvm-svn: 141142
* Teach TableGen to infer missing register classes.Jakob Stoklund Olesen2011-10-041-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The set of register classes should be closed under sub-register operations and intersections. That will allow the register allocator to model combinations of constraints accurately. This patch implements the easiest form of register class inference: For every register class, and for every sub-register SubIdx, the subset of registers in RC that have a SubIdx sub-register should also be a register class. This does create some new register classes for the targets in the tree: ARM gets a new QQQQPR_with_ssub_0. This class was omitted from the .td file on purpose because it only has two registers. InstrEmitter and RegisterCoalescer have safeguards against selecting too small register classes, so it is harmless. PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32 sub-register of LR8. I think that might be an omission? X86 puts RIP in the GR64 class, and since that register doesn't have 8-bit sub-registers, we get: GR64_with_sub_8bit GR64_TC_with_sub_8bit GR64_NOREX_with_sub_8bit GR64_TC_with_sub_8bit_hi The various CodeGen classes have already been fixed so adding new register classes should not affect compile time. llvm-svn: 141084
* TableGen: Store all allocation orders together.Jakob Stoklund Olesen2011-10-041-7/+4
| | | | | | There is no need to keep the primary order separate. llvm-svn: 141082
* TableGen: Privatize CodeGenRegisterClass::TheDef and Name.Jakob Stoklund Olesen2011-10-041-2/+8
| | | | | | | | When TableGen starts creating its own register classes, the synthesized classes won't have a Record reference. All register classes must have a name, though. llvm-svn: 141081
* Move TableGen's parser and entry point into a libraryPeter Collingbourne2011-10-011-1/+1
| | | | | | This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
* Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().Jakob Stoklund Olesen2011-09-301-1/+7
| | | | | | | All the sub-class bit vectors are computed when first creating the register bank. llvm-svn: 140905
* Compute lists of super-classes in CodeGenRegisterClass.Jakob Stoklund Olesen2011-09-301-0/+14
| | | | | | | Use these lists instead of computing them on the fly in RegisterInfoEmitter. llvm-svn: 140895
* Precompute a bit vector of register sub-classes.Jakob Stoklund Olesen2011-09-301-0/+6
| | | | llvm-svn: 140827
* Order register classes topologically.Jakob Stoklund Olesen2011-09-301-0/+1
| | | | | | | | | All register classes are given a lower ID than their sub-classes. Cliques are ordered alphabetically. This will be used to simplify some sub-class operations. llvm-svn: 140826
* Switch to ArrayRef<CodeGenRegisterClass*>.Jakob Stoklund Olesen2011-09-291-2/+2
| | | | | | | This makes it possible to allocate CodeGenRegisterClass instances dynamically and reorder them. llvm-svn: 140816
* Store CodeGenRegisters as pointers so they won't be reallocated.Jakob Stoklund Olesen2011-06-181-2/+2
| | | | | | | Reuse the CodeGenRegBank DenseMap in a few places that would build their own or use linear search. llvm-svn: 133333
* Remove MethodProtos/MethodBodies and allocation_order_begin/end.Jakob Stoklund Olesen2011-06-181-1/+1
| | | | | | | | | | | | | | Targets that need to change the default allocation order should use the AltOrders mechanism instead. See the X86 and ARM targets for examples. The allocation_order_begin() and allocation_order_end() methods have been replaced with getRawAllocationOrder(), and there is further support functions in RegisterClassInfo. It is no longer possible to insert arbitrary code into generated register classes. This is a feature. llvm-svn: 133332
* Provide AltOrders for specifying alternative allocation orders.Jakob Stoklund Olesen2011-06-181-3/+11
| | | | | | | | | | | | A register class can define AltOrders and AltOrderSelect instead of defining method protos and bodies. The AltOrders lists can be defined with set operations, and TableGen can verify that the alternative allocation orders only contain valid registers. This is currently an opt-in feature, and it is still possible to override allocation_order_begin/end. That will not be true for long. llvm-svn: 133320
* Use a SetTheory instance to expand register lists in register classes.Jakob Stoklund Olesen2011-06-151-2/+7
| | | | | | | | This prepares tablegen to compute register lists from set theoretic dag expressions. This doesn't really make any difference as long as Target.td still declares RegisterClass::MemberList as [Register]. llvm-svn: 133043
* Give CodeGenRegisterClass a real sorted member set.Jakob Stoklund Olesen2011-06-151-30/+17
| | | | | | | | | | | Make the Elements vector private and expose an ArrayRef through getOrder() instead. getOrder will eventually provide multiple user-specified allocation orders. Use the sorted member set for member and subclass tests. Clean up a lot of ad hoc searches. llvm-svn: 133040
* Move the list of register classes into CodeGenRegBank as well.Jakob Stoklund Olesen2011-06-151-0/+17
| | | | | | No functional change intended. llvm-svn: 133029
* Compute lists of sub-regs, super-regs, and overlapping regs.Jakob Stoklund Olesen2011-06-121-0/+34
| | | | | | | | | | | | | | | | | | | | | | | Besides moving structural computations to CodeGenRegisters.cpp, this also well-defines the order of these lists: - Sub-register lists come from a pre-order traversal of the graph defined by the SubRegs lists in the .td files. - Super-register lists are topologically ordered so no register comes before any of its sub-registers. When the sub-register graph is not a tree, independent super-registers appear in numerical order. - Lists of overlapping registers are ordered according to register number. This reverses the order of the super-regs lists, but nobody was depending on that. The previous order of the overlaps lists was odd, and it may have depended on the precise behavior of std::stable_sort. The old computations are still there, but will be removed shortly. llvm-svn: 132881
* Move the list of registers into CodeGenRegBank.Jakob Stoklund Olesen2011-06-111-14/+48
| | | | | | | Also move the sub-register index computations from RegisterInfoEmitter into CodeGenRegBank. llvm-svn: 132865
* Move some sub-register index calculations to CodeGenRegisters.cppJakob Stoklund Olesen2011-06-101-0/+27
| | | | | | | Create a new CodeGenRegBank class that will eventually hold all the code that computes the register structure from Records. llvm-svn: 132849
* Make it possible to have unallocatable register classes.Jakob Stoklund Olesen2011-06-021-0/+1
| | | | | | | | | | | | | | | Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. llvm-svn: 132508
* Don't allow per-register spill size and alignment.Jakob Stoklund Olesen2011-04-211-1/+0
| | | | | | | These values were not used for anything. Spill size and alignment is a property of the register class, not the register. llvm-svn: 129906
* Prefer cheap registers for busy live ranges.Jakob Stoklund Olesen2011-04-201-0/+1
| | | | | | | | | | | | | | On the x86-64 and thumb2 targets, some registers are more expensive to encode than others in the same register class. Add a CostPerUse field to the TableGen register description, and make it available from TRI->getCostPerUse. This represents the cost of a REX prefix or a 32-bit instruction encoding required by choosing a high register. Teach the greedy register allocator to prefer cheap registers for busy live ranges (as indicated by spill weight). llvm-svn: 129864
* Make the register enum value part of the CodeGenRegister struct.Jim Grosbach2011-03-111-0/+1
| | | | llvm-svn: 127448
* Trailing whitespace.Jim Grosbach2011-03-111-4/+4
| | | | llvm-svn: 127446
* add (and document) the ability for alias results to haveChris Lattner2010-11-061-0/+6
| | | | | | | | fixed physical registers. Start moving fp comparison aliases to the .td file (which default to using %st1 if nothing is specified). llvm-svn: 118352
* Split out register class subclassing to a separate function and clean upEric Christopher2010-08-251-0/+32
| | | | | | accordingly. No functional change. llvm-svn: 112008
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-1/+3
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-3/+3
| | | | | | | | while the latter is capable of representing either a primitive or an extended type. llvm-svn: 78713
OpenPOWER on IntegriCloud