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authorAndrew Trick <atrick@apple.com>2012-04-10 02:25:18 +0000
committerAndrew Trick <atrick@apple.com>2012-04-10 02:25:18 +0000
commit3a6e88dcc95411f13cb27e6220d09531b2b5167c (patch)
treef5adb0b2c2403851f8fdea59178a481ccf870395 /llvm/utils/TableGen/CodeGenRegisters.h
parent549515e12893e066f5bfb20de7b520cd1899b236 (diff)
downloadbcm5719-llvm-3a6e88dcc95411f13cb27e6220d09531b2b5167c.tar.gz
bcm5719-llvm-3a6e88dcc95411f13cb27e6220d09531b2b5167c.zip
Fix header comment
llvm-svn: 154372
Diffstat (limited to 'llvm/utils/TableGen/CodeGenRegisters.h')
-rw-r--r--llvm/utils/TableGen/CodeGenRegisters.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/utils/TableGen/CodeGenRegisters.h b/llvm/utils/TableGen/CodeGenRegisters.h
index f73519ebbf7..0d26bc493e4 100644
--- a/llvm/utils/TableGen/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/CodeGenRegisters.h
@@ -116,8 +116,8 @@ namespace llvm {
// List of super-registers in topological order, small to large.
typedef std::vector<const CodeGenRegister*> SuperRegList;
- // Get the list of super-registers.
- // This is only valid after computeDerivedInfo has visited all registers.
+ // Get the list of super-registers. This is valid after getSubReg
+ // visits all registers during RegBank construction.
const SuperRegList &getSuperRegs() const {
assert(SubRegsComplete && "Must precompute sub-registers");
return SuperRegs;
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