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* Make "mov" work for all Thumb2 MOV encodingsMihai Popa2013-08-211-1/+16
| | | | | | | According to the ARM specification, "mov" is a valid mnemonic for all Thumb2 MOV encodings. To achieve this, the patch adds one instruction alias with a special range condition to avoid collision with the Thumb1 MOV. llvm-svn: 188901
* AVX-512: Added SHIFT instructions.Elena Demikhovsky2013-08-212-0/+124
| | | | llvm-svn: 188899
* [SystemZ] Define remainig *MUL_LOHI patternsRichard Sandiford2013-08-212-3/+63
| | | | | | | | | | | | | | | | | The initial port used MLG(R) for i64 UMUL_LOHI but left the other three combinations as not-legal-or-custom. Although 32x32->{32,32} multiplications exist, they're not as quick as doing a normal 64-bit multiplication, so it didn't seem like i32 SMUL_LOHI and UMUL_LOHI would be useful. There's also no direct instruction for i64 SMUL_LOHI, so it needs to be implemented in terms of UMUL_LOHI. However, not defining these patterns means that we don't convert division by a constant into multiplication, so this patch fills in the other cases. The new i64 SMUL_LOHI sequence is simpler than the one that we used previously for 64x64->128 multiplication, so int-mul-08.ll now tests the full sequence. llvm-svn: 188898
* [SystemZ] Use FI[EDX]BRA for codegenRichard Sandiford2013-08-212-6/+315
| | | | llvm-svn: 188895
* [SystemZ] Add FI[EDX]BRARichard Sandiford2013-08-214-0/+159
| | | | | | | These are extensions of the existing FI[EDX]BR instructions, but use a spare bit to suppress inexact conditions. llvm-svn: 188894
* MC: ObjectSymbolizer can now recognize external function stubs.Ahmed Bougacha2013-08-212-0/+18
| | | | | | | Only implemented in the Mach-O ObjectSymbolizer. The testcase sadly introduces a new binary. llvm-svn: 188879
* DebugInfo: Do not use the DWARF Version for the .debug_pubnames or ↵David Majnemer2013-08-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | .debug_pubtypes version field Summary: LLVM would generate DWARF with version 3 in the .debug_pubname and .debug_pubtypes version fields. This would lead SGI dwarfdump to fail parsing the DWARF with (in the instance of .debug_pubnames) would exit with: dwarfdump ERROR: dwarf_get_globals: DW_DLE_PUBNAMES_VERSION_ERROR (123) This fixes PR16950. Reviewers: echristo, dblaikie Reviewed By: echristo CC: cfe-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1454 llvm-svn: 188869
* In LLVM FMA3 operands are dst, src1, src2, src3, however dst is not encoded ↵Nadav Rotem2013-08-211-0/+18
| | | | | | | | as it is always src1. This was causing the encoding of the operands to be off by one. Patch by Chris Bieneman. llvm-svn: 188866
* Add the FMA3 feature in order to test FMA encoding using the old jit.Nadav Rotem2013-08-211-0/+10
| | | | | | Patch by Chris Bieneman! llvm-svn: 188865
* X86TargetMachine.cpp: Clarify to emit GOT in i686-{cygming|win32}-elf for mcjit.NAKAMURA Takumi2013-08-214-4/+4
| | | | | | I suppose all "lli -use-mcjit i686-*" should require GOT, (and to fail.) llvm-svn: 188856
* [micromips] Print instruction alias "not" if the last operand of a nor is zero.Akira Hatanaka2013-08-211-2/+2
| | | | llvm-svn: 188851
* [mips] Add support for mfhc1 and mthc1.Akira Hatanaka2013-08-201-6/+17
| | | | llvm-svn: 188848
* Use -disable-output and to suppress output and don't use a temporary file ↵Bill Wendling2013-08-205-7/+5
| | | | | | unless we need one. llvm-svn: 188843
* SLPVectorizer: Fix invalid iterator errorsArnold Schwaighofer2013-08-201-0/+30
| | | | | | | | | | | Update iterator when the SLP vectorizer changes the instructions in the basic block by restarting the traversal of the basic block. Patch by Yi Jiang! Fixes PR 16899. llvm-svn: 188832
* Teach ConstantFolding about pointer address spacesMatt Arsenault2013-08-204-4/+531
| | | | llvm-svn: 188831
* Add an option which permits the user to specify using a bitmask, that variousReed Kotler2013-08-201-0/+23
| | | | | | | | | functions be compiled as mips32, without having to add attributes. This is useful in certain situations where you don't want to have to edit the function attributes in the source. For now it's only an option used for the compiler developers when debugging the mips16 port. llvm-svn: 188826
* [mips] Guard micromips instructions with predicate InMicroMips. Also, fixAkira Hatanaka2013-08-201-2/+2
| | | | | | assembler predicate HasStdEnd so that it is false when the target is micromips. llvm-svn: 188824
* ARM: Fix fast-isel copy/paste-o.Jim Grosbach2013-08-201-5/+6
| | | | | | | | | | | | Update testcase to be more careful about checking register values. While regexes are general goodness for these sorts of testcases, in this example, the registers are constrained by the calling convention, so we can and should check their explicit values. rdar://14779513 llvm-svn: 188819
* Still more MCJIT PIC test XFAILsAndrew Kaylor2013-08-203-3/+3
| | | | llvm-svn: 188815
* Clarifying two MCJIT PIC tests as XFAIL on i686-pc-linuxAndrew Kaylor2013-08-204-4/+4
| | | | llvm-svn: 188814
* Removing duplicate XFAIL markersAndrew Kaylor2013-08-202-2/+2
| | | | llvm-svn: 188812
* Marking two more MCJIT PIC tests as XFAIL on i686Andrew Kaylor2013-08-204-4/+4
| | | | llvm-svn: 188808
* Marking MCJIT PIC tests as XFAIL on armAndrew Kaylor2013-08-206-6/+6
| | | | llvm-svn: 188807
* AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQElena Demikhovsky2013-08-201-0/+27
| | | | llvm-svn: 188786
* [mips][msa] Removed fcge, fcgt, fsge, fsgtDaniel Sanders2013-08-201-176/+0
| | | | | | | These instructions were present in a draft spec but were removed before publication. llvm-svn: 188782
* [SystemZ] Use SRST to optimize memchrRichard Sandiford2013-08-202-0/+78
| | | | | | | | | | | | | | | | | | | SystemZTargetLowering::emitStringWrapper() previously loaded the character into R0 before the loop and made R0 live on entry. I'd forgotten that allocatable registers weren't allowed to be live across blocks at this stage, and it confused LiveVariables enough to cause a miscompilation of f3 in memchr-02.ll. This patch instead loads R0 in the loop and leaves LICM to hoist it after RA. This is actually what I'd tried originally, but I went for the manual optimisation after noticing that R0 often wasn't being hoisted. This bug forced me to go back and look at why, now fixed as r188774. We should also try to optimize null checks so that they test the CC result of the SRST directly. The select between null and the SRST GPR result could then usually be deleted as dead. llvm-svn: 188779
* [mips][msa] Added insveDaniel Sanders2013-08-201-0/+91
| | | | llvm-svn: 188777
* Fix test typo and add usual "br %r14" testRichard Sandiford2013-08-201-1/+2
| | | | llvm-svn: 188775
* Fix overly pessimistic shortcut in post-RA MachineLICMRichard Sandiford2013-08-201-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Post-RA LICM keeps three sets of registers: PhysRegDefs, PhysRegClobbers and TermRegs. When it sees a definition of R it adds all aliases of R to the corresponding set, so that when it needs to test for membership it only needs to test a single register, rather than worrying about aliases there too. E.g. the final candidate loop just has: unsigned Def = Candidates[i].Def; if (!PhysRegClobbers.test(Def) && ...) { to test whether register Def is multiply defined. However, there was also a shortcut in ProcessMI to make sure we didn't add candidates if we already knew that they would fail the final test. This shortcut was more pessimistic than the final one because it checked whether _any alias_ of the defined register was multiply defined. This is too conservative for targets that define register pairs. E.g. on z, R0 and R1 are sometimes used as a pair, so there is a 128-bit register that aliases both R0 and R1. If a loop used R0 and R1 independently, and the definition of R0 came first, we would be able to hoist the R0 assignment (because that used the final test quoted above) but not the R1 assignment (because that meant we had two definitions of the paired R0/R1 register and would fail the shortcut in ProcessMI). This patch just uses the same check for the ProcessMI shortcut as we use in the final candidate loop. llvm-svn: 188774
* ARM: implement some simple f64 materializations.Tim Northover2013-08-202-3/+70
| | | | | | | | Previously we used a const-pool load for virtually all 64-bit floating values. Actually, we can get quite a few common values (including 0.0, 1.0) via "vmov" instructions of one stripe or another. llvm-svn: 188773
* [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.vDaniel Sanders2013-08-201-0/+176
| | | | llvm-svn: 188767
* Marking MCJIT PIC tests as XFAIL on AArch64Andrew Kaylor2013-08-209-9/+9
| | | | llvm-svn: 188740
* Fixing XPASSes among MCJIT PIC test on i686Andrew Kaylor2013-08-204-4/+4
| | | | llvm-svn: 188736
* Second attempt to mark Large/PIC MCJIT test as XFAIL for PowerPC64Andrew Kaylor2013-08-201-1/+1
| | | | llvm-svn: 188735
* Marking two MCJIT PIC tests as XFAIL on DarwinAndrew Kaylor2013-08-202-2/+2
| | | | llvm-svn: 188734
* Trying again with PIC tests for MCJITAndrew Kaylor2013-08-199-0/+252
| | | | llvm-svn: 188730
* Add a llvm.copysign intrinsicHal Finkel2013-08-191-0/+53
| | | | | | | | | | | | | | | | | | | | | This adds a llvm.copysign intrinsic; We already have Libfunc recognition for copysign (which is turned into the FCOPYSIGN SDAG node). In order to autovectorize calls to copysign in the loop vectorizer, we need a corresponding intrinsic as well. In addition to the expected changes to the language reference, the loop vectorizer, BasicTTI, and the SDAG builder (the intrinsic is transformed into an FCOPYSIGN node, just like the function call), this also adds FCOPYSIGN to a few lists in LegalizeVector{Ops,Types} so that vector copysigns can be expanded. In TargetLoweringBase::initActions, I've made the default action for FCOPYSIGN be Expand for vector types. This seems correct for all in-tree targets, and I think is the right thing to do because, previously, there was no way to generate vector-values FCOPYSIGN nodes (and most targets don't specify an action for vector-typed FCOPYSIGN). llvm-svn: 188728
* Don't form PPC CTR-based loops around a copysignl callHal Finkel2013-08-191-0/+28
| | | | | | | | | copysign/copysignf never become function calls (because the SDAG expansion code does not lower to the corresponding function call, but rather directly implements the associated logic), but copysignl almost always is lowered into a call to the requested libm functon (and, thus, might clobber CTR). llvm-svn: 188727
* Teach InstCombine visitGetElementPtr about address spacesMatt Arsenault2013-08-191-1/+28
| | | | llvm-svn: 188721
* Reverting r188709 until I can figure out the proper way to XFAIL it.Andrew Kaylor2013-08-199-252/+0
| | | | llvm-svn: 188715
* Fix assert with GEP ptr vector indexing structsMatt Arsenault2013-08-191-0/+11
| | | | | | | | Also fix it calculating the wrong value. The struct index is not a ConstantInt, so it was being interpreted as an array index. llvm-svn: 188713
* Revert non-test parts of r188507Matt Arsenault2013-08-191-1/+65
| | | | | | Re-add the inboundsless tests I didn't add originally llvm-svn: 188710
* Adding tests for PIC with MCJITAndrew Kaylor2013-08-199-0/+252
| | | | llvm-svn: 188709
* Turn on pubnames by default on linux.Eric Christopher2013-08-192-1/+131
| | | | | | | | | Until gdb supports the new accelerator tables we should add the pubnames section so that gdb_index can be generated from gold at link time. On darwin we already emit the accelerator tables and so don't need to worry about pubnames. llvm-svn: 188708
* Improve the widening of integral binary vector operationsPaul Redmond2013-08-193-10/+4
| | | | | | | | | | | | | | - split WidenVecRes_Binary into WidenVecRes_Binary and WidenVecRes_BinaryCanTrap - WidenVecRes_BinaryCanTrap preserves the original behaviour for operations that can trap - WidenVecRes_Binary simply widens the operation and improves codegen for 3-element vectors by allowing widening and promotion on x86 (matches the behaviour of unary and ternary operation widening) - use WidenVecRes_Binary for operations on integers. Reviewed by: nrotem llvm-svn: 188699
* [mips] Fix instruction definitions that were incorrectly marked as ↵Akira Hatanaka2013-08-191-0/+1
| | | | | | code-gen-only. llvm-svn: 188690
* Thumb2 add immediate alias for SPMihai Popa2013-08-191-0/+2
| | | | | | | | The Thumb2 add immediate is in fact defined for SP. The manual is misleading as it points to a different section for add immediate with SP, however the encoding is the same as for add immediate with register only with the SP operand hard coded. As such add immediate with SP and add immediate with register can safely be treated as the same instruction. All the patch does is adjust a register constraint on an instruction alias. llvm-svn: 188676
* AVX-512: added arithmetic and logical operations.Elena Demikhovsky2013-08-192-3/+229
| | | | | | | ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. llvm-svn: 188673
* [SystemZ] Add negative integer absolute (load negative)Richard Sandiford2013-08-193-0/+157
| | | | | | | | For now this matches the equivalent of (neg (abs ...)), which did hit a few times in projects/test-suite. We should probably also match cases where absolute-like selects are used with reversed arguments. llvm-svn: 188671
* [SystemZ] Add integer absolute (load positive)Richard Sandiford2013-08-193-0/+149
| | | | llvm-svn: 188670
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