[mips][msa] Removed fcge, fcgt, fsge, fsgt

These instructions were present in a draft spec but were removed before
publication.

llvm-svn: 188782

1 files changed, 0 insertions, 176 deletions

diff --git a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
index 70f73f5777e..112f1177b90 100644
--- a/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
+++ b/llvm/test/CodeGen/Mips/msa/3rf_int_float.ll
@@ -44,94 +44,6 @@ declare <2 x i64> @llvm.mips.fceq.d(<2 x double>, <2 x double>) nounwind
 ; CHECK: st.d
 ; CHECK: .size llvm_mips_fceq_d_test
 ;
-@llvm_mips_fcge_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
-@llvm_mips_fcge_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
-@llvm_mips_fcge_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
-
-define void @llvm_mips_fcge_w_test() nounwind {
-entry:
-  %0 = load <4 x float>* @llvm_mips_fcge_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fcge_w_ARG2
-  %2 = tail call <4 x i32> @llvm.mips.fcge.w(<4 x float> %0, <4 x float> %1)
-  store <4 x i32> %2, <4 x i32>* @llvm_mips_fcge_w_RES
-  ret void
-}
-
-declare <4 x i32> @llvm.mips.fcge.w(<4 x float>, <4 x float>) nounwind
-
-; CHECK: llvm_mips_fcge_w_test:
-; CHECK: ld.w
-; CHECK: ld.w
-; CHECK: fcge.w
-; CHECK: st.w
-; CHECK: .size llvm_mips_fcge_w_test
-;
-@llvm_mips_fcge_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
-@llvm_mips_fcge_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
-@llvm_mips_fcge_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
-
-define void @llvm_mips_fcge_d_test() nounwind {
-entry:
-  %0 = load <2 x double>* @llvm_mips_fcge_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fcge_d_ARG2
-  %2 = tail call <2 x i64> @llvm.mips.fcge.d(<2 x double> %0, <2 x double> %1)
-  store <2 x i64> %2, <2 x i64>* @llvm_mips_fcge_d_RES
-  ret void
-}
-
-declare <2 x i64> @llvm.mips.fcge.d(<2 x double>, <2 x double>) nounwind
-
-; CHECK: llvm_mips_fcge_d_test:
-; CHECK: ld.d
-; CHECK: ld.d
-; CHECK: fcge.d
-; CHECK: st.d
-; CHECK: .size llvm_mips_fcge_d_test
-;
-@llvm_mips_fcgt_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
-@llvm_mips_fcgt_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
-@llvm_mips_fcgt_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
-
-define void @llvm_mips_fcgt_w_test() nounwind {
-entry:
-  %0 = load <4 x float>* @llvm_mips_fcgt_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fcgt_w_ARG2
-  %2 = tail call <4 x i32> @llvm.mips.fcgt.w(<4 x float> %0, <4 x float> %1)
-  store <4 x i32> %2, <4 x i32>* @llvm_mips_fcgt_w_RES
-  ret void
-}
-
-declare <4 x i32> @llvm.mips.fcgt.w(<4 x float>, <4 x float>) nounwind
-
-; CHECK: llvm_mips_fcgt_w_test:
-; CHECK: ld.w
-; CHECK: ld.w
-; CHECK: fcgt.w
-; CHECK: st.w
-; CHECK: .size llvm_mips_fcgt_w_test
-;
-@llvm_mips_fcgt_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
-@llvm_mips_fcgt_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
-@llvm_mips_fcgt_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
-
-define void @llvm_mips_fcgt_d_test() nounwind {
-entry:
-  %0 = load <2 x double>* @llvm_mips_fcgt_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fcgt_d_ARG2
-  %2 = tail call <2 x i64> @llvm.mips.fcgt.d(<2 x double> %0, <2 x double> %1)
-  store <2 x i64> %2, <2 x i64>* @llvm_mips_fcgt_d_RES
-  ret void
-}
-
-declare <2 x i64> @llvm.mips.fcgt.d(<2 x double>, <2 x double>) nounwind
-
-; CHECK: llvm_mips_fcgt_d_test:
-; CHECK: ld.d
-; CHECK: ld.d
-; CHECK: fcgt.d
-; CHECK: st.d
-; CHECK: .size llvm_mips_fcgt_d_test
-;
 @llvm_mips_fcle_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
 @llvm_mips_fcle_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
 @llvm_mips_fcle_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
@@ -352,94 +264,6 @@ declare <2 x i64> @llvm.mips.fseq.d(<2 x double>, <2 x double>) nounwind
 ; CHECK: st.d
 ; CHECK: .size llvm_mips_fseq_d_test
 ;
-@llvm_mips_fsge_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
-@llvm_mips_fsge_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
-@llvm_mips_fsge_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
-
-define void @llvm_mips_fsge_w_test() nounwind {
-entry:
-  %0 = load <4 x float>* @llvm_mips_fsge_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsge_w_ARG2
-  %2 = tail call <4 x i32> @llvm.mips.fsge.w(<4 x float> %0, <4 x float> %1)
-  store <4 x i32> %2, <4 x i32>* @llvm_mips_fsge_w_RES
-  ret void
-}
-
-declare <4 x i32> @llvm.mips.fsge.w(<4 x float>, <4 x float>) nounwind
-
-; CHECK: llvm_mips_fsge_w_test:
-; CHECK: ld.w
-; CHECK: ld.w
-; CHECK: fsge.w
-; CHECK: st.w
-; CHECK: .size llvm_mips_fsge_w_test
-;
-@llvm_mips_fsge_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
-@llvm_mips_fsge_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
-@llvm_mips_fsge_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
-
-define void @llvm_mips_fsge_d_test() nounwind {
-entry:
-  %0 = load <2 x double>* @llvm_mips_fsge_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsge_d_ARG2
-  %2 = tail call <2 x i64> @llvm.mips.fsge.d(<2 x double> %0, <2 x double> %1)
-  store <2 x i64> %2, <2 x i64>* @llvm_mips_fsge_d_RES
-  ret void
-}
-
-declare <2 x i64> @llvm.mips.fsge.d(<2 x double>, <2 x double>) nounwind
-
-; CHECK: llvm_mips_fsge_d_test:
-; CHECK: ld.d
-; CHECK: ld.d
-; CHECK: fsge.d
-; CHECK: st.d
-; CHECK: .size llvm_mips_fsge_d_test
-;
-@llvm_mips_fsgt_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
-@llvm_mips_fsgt_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
-@llvm_mips_fsgt_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
-
-define void @llvm_mips_fsgt_w_test() nounwind {
-entry:
-  %0 = load <4 x float>* @llvm_mips_fsgt_w_ARG1
-  %1 = load <4 x float>* @llvm_mips_fsgt_w_ARG2
-  %2 = tail call <4 x i32> @llvm.mips.fsgt.w(<4 x float> %0, <4 x float> %1)
-  store <4 x i32> %2, <4 x i32>* @llvm_mips_fsgt_w_RES
-  ret void
-}
-
-declare <4 x i32> @llvm.mips.fsgt.w(<4 x float>, <4 x float>) nounwind
-
-; CHECK: llvm_mips_fsgt_w_test:
-; CHECK: ld.w
-; CHECK: ld.w
-; CHECK: fsgt.w
-; CHECK: st.w
-; CHECK: .size llvm_mips_fsgt_w_test
-;
-@llvm_mips_fsgt_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16
-@llvm_mips_fsgt_d_ARG2 = global <2 x double> <double 2.000000e+00, double 3.000000e+00>, align 16
-@llvm_mips_fsgt_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
-
-define void @llvm_mips_fsgt_d_test() nounwind {
-entry:
-  %0 = load <2 x double>* @llvm_mips_fsgt_d_ARG1
-  %1 = load <2 x double>* @llvm_mips_fsgt_d_ARG2
-  %2 = tail call <2 x i64> @llvm.mips.fsgt.d(<2 x double> %0, <2 x double> %1)
-  store <2 x i64> %2, <2 x i64>* @llvm_mips_fsgt_d_RES
-  ret void
-}
-
-declare <2 x i64> @llvm.mips.fsgt.d(<2 x double>, <2 x double>) nounwind
-
-; CHECK: llvm_mips_fsgt_d_test:
-; CHECK: ld.d
-; CHECK: ld.d
-; CHECK: fsgt.d
-; CHECK: st.d
-; CHECK: .size llvm_mips_fsgt_d_test
-;
 @llvm_mips_fsle_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16
 @llvm_mips_fsle_w_ARG2 = global <4 x float> <float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00>, align 16
 @llvm_mips_fsle_w_RES  = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16