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| author | Paul Redmond <paul.redmond@intel.com> | 2013-08-19 20:01:35 +0000 |
|---|---|---|
| committer | Paul Redmond <paul.redmond@intel.com> | 2013-08-19 20:01:35 +0000 |
| commit | 62f840f46a0b714d75beb42743a2d8080c9f265f (patch) | |
| tree | 07853b1f9a9f24a9ff7be46f8a7b52fdd6831362 /llvm/test | |
| parent | f2bef0b15dc7caf0864c906c707cb64449dd012b (diff) | |
| download | bcm5719-llvm-62f840f46a0b714d75beb42743a2d8080c9f265f.tar.gz bcm5719-llvm-62f840f46a0b714d75beb42743a2d8080c9f265f.zip | |
Improve the widening of integral binary vector operations
- split WidenVecRes_Binary into WidenVecRes_Binary and WidenVecRes_BinaryCanTrap
- WidenVecRes_BinaryCanTrap preserves the original behaviour for operations
that can trap
- WidenVecRes_Binary simply widens the operation and improves codegen for
3-element vectors by allowing widening and promotion on x86 (matches the
behaviour of unary and ternary operation widening)
- use WidenVecRes_Binary for operations on integers.
Reviewed by: nrotem
llvm-svn: 188699
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/X86/vsplit-and.ll | 2 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/widen_arith-3.ll | 4 | ||||
| -rw-r--r-- | llvm/test/CodeGen/X86/widen_load-2.ll | 8 |
3 files changed, 4 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/X86/vsplit-and.ll b/llvm/test/CodeGen/X86/vsplit-and.ll index 3b7fdff84e3..c16b2949358 100644 --- a/llvm/test/CodeGen/X86/vsplit-and.ll +++ b/llvm/test/CodeGen/X86/vsplit-and.ll @@ -14,7 +14,7 @@ define void @t0(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind read define void @t2(<3 x i64>* %dst, <3 x i64> %src1, <3 x i64> %src2) nounwind readonly { ; CHECK: t2 -; CHECK-NOT: pand +; CHECK: pand ; CHECK: ret %cmp1 = icmp ne <3 x i64> %src1, zeroinitializer %cmp2 = icmp ne <3 x i64> %src2, zeroinitializer diff --git a/llvm/test/CodeGen/X86/widen_arith-3.ll b/llvm/test/CodeGen/X86/widen_arith-3.ll index d86042a4480..cf6346bfe28 100644 --- a/llvm/test/CodeGen/X86/widen_arith-3.ll +++ b/llvm/test/CodeGen/X86/widen_arith-3.ll @@ -1,7 +1,5 @@ ; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+sse42 -post-RA-scheduler=true | FileCheck %s -; CHECK: incl -; CHECK: incl -; CHECK: incl +; CHECK: paddd ; Widen a v3i16 to v8i16 to do a vector add diff --git a/llvm/test/CodeGen/X86/widen_load-2.ll b/llvm/test/CodeGen/X86/widen_load-2.ll index f0f94e47921..2f203498fdb 100644 --- a/llvm/test/CodeGen/X86/widen_load-2.ll +++ b/llvm/test/CodeGen/X86/widen_load-2.ll @@ -73,9 +73,7 @@ define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) { ; CHECK: add3i16 %i16vec3 = type <3 x i16> define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind { -; CHECK: addl -; CHECK: addl -; CHECK: addl +; CHECK: paddd ; CHECK: ret %a = load %i16vec3* %ap, align 16 %b = load %i16vec3* %bp, align 16 @@ -135,9 +133,7 @@ define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* ; CHECK: add3i8 %i8vec3 = type <3 x i8> define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind { -; CHECK: addb -; CHECK: addb -; CHECK: addb +; CHECK: paddd ; CHECK: ret %a = load %i8vec3* %ap, align 16 %b = load %i8vec3* %bp, align 16 |
