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* [AVX512] Prefer AVX512 VPACK instructions over AVX/AVX2 instructions when ↵Craig Topper2016-05-011-8/+8
| | | | | | VLX and BWI are supported. llvm-svn: 268189
* [SCEV] When printing via -analysis, dump loop dispositionSanjoy Das2016-05-011-0/+73
| | | | | | | | | | | There are currently some bugs in tree around SCEV caching an incorrect loop disposition. Printing out loop dispositions will let us write whitebox tests as those are fixed. The dispositions are printed as a list in "inside out" order, i.e. innermost loop first. llvm-svn: 268177
* [InstCombine][AVX2] Added VPERMD/VPERMPS shuffle combining placeholder tests.Simon Pilgrim2016-04-301-0/+87
| | | | | | For future support for VPERMD/VPERMPS to generic shuffles combines llvm-svn: 268166
* [InstCombine][AVX] Split off VPERMILVAR tests and added additional tests for ↵Simon Pilgrim2016-04-302-60/+124
| | | | | | UNDEF mask elements llvm-svn: 268159
* AMDGPU/SI: Remove wait state handling for SMRD in SIInsertWaitsTom Stellard2016-04-302-2/+4
| | | | | | This was supposed to be part of r268143. llvm-svn: 268154
* Reverting 268054 & 268063 as they caused PR27579.Amjad Aboud2016-04-3014-693/+34
| | | | llvm-svn: 268150
* [LowerGuardIntrinsics] Keep track of !make.implicit metadataSanjoy Das2016-04-301-0/+12
| | | | | | | | | | If a guard call being lowered by LowerGuardIntrinsics has the `!make.implicit` metadata attached, then reattach the metadata to the branch in the resulting expanded form of the intrinsic. This allows us to implement null checks as guards and still get the benefit of implicit null checks. llvm-svn: 268148
* Reroll loops with multiple IV and negative step part 3Lawrence Hu2016-04-301-0/+134
| | | | | | | | | | | | | | support multiple induction variables This patch enable loop reroll for the following case: for(int i=0; i<N; i += 2) { S += *a++; S += *a++; }; Differential Revision: http://reviews.llvm.org/D16550 llvm-svn: 268147
* AMDGPU/SI: Enable the post-ra schedulerTom Stellard2016-04-3026-99/+102
| | | | | | | | | | | | | | Summary: This includes a hazard recognizer implementation to replace some of the hazard handling we had during frame index elimination. Reviewers: arsenm Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18602 llvm-svn: 268143
* [LowerGuardIntrinsics] Preserve calling conv when loweringSanjoy Das2016-04-301-0/+15
| | | | llvm-svn: 268142
* add minimal test to show dropped metadataSanjay Patel2016-04-301-0/+28
| | | | llvm-svn: 268141
* remove the metadata added with r267827Sanjay Patel2016-04-301-14/+6
| | | | | | | We can demonstrate the 'select' bug and fix with a simpler test case. The merged weight values are already tested in another test. llvm-svn: 268139
* Mark guards on true as "trivially dead"Sanjoy Das2016-04-291-0/+11
| | | | | | | | | This moves some logic added to EarlyCSE in rL268120 into `llvm::isInstructionTriviallyDead`. Adds a test case for DCE to demonstrate that passes other than EarlyCSE can now pick up on the new information. llvm-svn: 268126
* [MBP] Use Function::optForSize() instead of checking OptimizeForSize directly.Haicheng Wu2016-04-292-0/+70
| | | | | | Fix a FIXME. Disable loop alignment if compiled with -Oz now. llvm-svn: 268121
* [EarlyCSE] Simplify guard intrinsicsSanjoy Das2016-04-291-0/+181
| | | | | | | | | | | | | | | | | | Summary: This change teaches EarlyCSE some basic properties of guard intrinsics: - Guard intrinsics read all memory, but don't write to any memory - After a guard has executed, the condition it was guarding on can be assumed to be true - Guard intrinsics on a constant `true` are no-ops Reviewers: reames, hfinkel Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19578 llvm-svn: 268120
* AMDGPU: Fix crash with unreachable terminators.Matt Arsenault2016-04-291-0/+56
| | | | | | | | | | If a block has no successors because it ends in unreachable, this was accessing an invalid iterator. Also stop counting instructions that don't emit any real instructions. llvm-svn: 268119
* Differential Revision: http://reviews.llvm.org/D19733Sriraman Tallam2016-04-294-12/+29
| | | | llvm-svn: 268106
* AMDGPU: Add kernarg.segment.ptr intrinsicMatt Arsenault2016-04-291-0/+21
| | | | llvm-svn: 268105
* [InstCombine] Determine the result of a select based on a dominating condition.Chad Rosier2016-04-291-0/+103
| | | | | | Differential Revision: http://reviews.llvm.org/D19550 llvm-svn: 268104
* DAGCombiner: Reduce truncated shl widthMatt Arsenault2016-04-2920-278/+414
| | | | llvm-svn: 268094
* [ValueTracking] matchSelectPattern needs to be more careful around FPDavid Majnemer2016-04-291-0/+26
| | | | | | | | | | | | matchSelectPattern attempts to see through casts which mask min/max patterns from being more obvious. Under certain circumstances, it would misidentify a sequence of instructions as a min/max because it assumed that folding casts would preserve the result. This is not the case for floating point <-> integer casts. This fixes PR27575. llvm-svn: 268086
* [AMDGPU][llvm-mc] Add some missing testcases to trap.sArtem Tamazov2016-04-291-0/+25
| | | | | | Differential Revision: http://reviews.llvm.org/D19602 llvm-svn: 268073
* [BasicAA] Treat llvm.assume as not accessing memory in ↵Geoff Berry2016-04-291-0/+17
| | | | | | | | | | | | getModRefBehavior(Function) Reviewers: dberlin, chandlerc, hfinkel, reames, sanjoy Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D19730 llvm-svn: 268068
* Fixed/Recommitted r267733 "[AMDGPU][llvm-mc] Add support of TTMP quads. ↵Artem Tamazov2016-04-293-0/+108
| | | | | | | | | | | Rework M0 exclusion for SMRD." Previously reverted by r267752. r267733 review: Differential Revision: http://reviews.llvm.org/D19342 llvm-svn: 268066
* [PPC] Enable shuffling of VSX vectorsGuozhi Wei2016-04-291-0/+15
| | | | | | This patch fixes PR27078 by enabling shuffling of vectors if VSX is available. llvm-svn: 268064
* Fixed LIT tests that was broken after change in r268054.Amjad Aboud2016-04-291-4/+0
| | | | llvm-svn: 268063
* auto-generate checksSanjay Patel2016-04-291-43/+40
| | | | llvm-svn: 268061
* [mips][ias] Move createCpRestoreMemOp to MipsTargetStreamer. NFC.Daniel Sanders2016-04-291-4/+20
| | | | | | | | | | | | | | | Summary: This removes the temporary call to isIntegratedAssemblerRequired() which was added recently. It's effect is now acheived directly in the MipsTargetStreamer hierarchy. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19715 llvm-svn: 268058
* Recommitted r264280 "Supporting all entities declared in lexical scope in ↵Amjad Aboud2016-04-2913-30/+693
| | | | | | | | LLVM debug info." After fixing PR26942 in r267004. llvm-svn: 268054
* [mips][FastISel] A store is not a load.Simon Dardis2016-04-291-1/+1
| | | | | | | | | | Correct trivial error. One of the failing tests from PR/27458. Reviewers: dsanders, vkalintiris, mcrosier Differential Review: http://reviews.llvm.org/D19726 llvm-svn: 268053
* [Hexagon] Optimize addressing modes for load/storeKrzysztof Parzyszek2016-04-294-12/+124
| | | | | | Patch by Jyotsna Verma. llvm-svn: 268051
* AMDGPU/SI: Add offset field to ds_permute/ds_bpermute instructionsTom Stellard2016-04-292-1/+21
| | | | | | | | | | | | | | Summary: These instructions can add an immediate offset to the address, like other ds instructions. Reviewers: arsenm Subscribers: arsenm, scchan Differential Revision: http://reviews.llvm.org/D19233 llvm-svn: 268043
* [mips][ias] Split expandMemInst between MipsAsmParser and ↵Daniel Sanders2016-04-292-2/+2
| | | | | | | | | | | | | | | | | | | | | | MipsTargetStreamer. Almost NFC. Summary: The portion in MipsAsmParser is responsible for figuring out which expansion to use, while the portion in MipsTargetStreamer is responsible for emitting it. This allows us to remove the call to isIntegratedAssemblerRequired() which is currently ensuring the effect of .cprestore only occurs when writing objects. The small functional change is that the memory offsets are now correctly printed as signed values. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19714 llvm-svn: 268042
* [mips][ias] Make section sizes a multiple of the alignment.Daniel Sanders2016-04-292-1/+107
| | | | | | | | | | Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19008 llvm-svn: 268036
* [InstCombine][SSE] Added x86 pshufb undef mask testsSimon Pilgrim2016-04-291-1/+37
| | | | | FIXME: We currently don't support folding constant pshufb shuffle masks containing undef elements. llvm-svn: 268016
* AMDGPU/SI: Assembler: Unify parsing/printing of operands.Nikolay Haustov2016-04-2931-353/+352
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The goal is for each operand type to have its own parse function and at the same time share common code for tracking state as different instruction types share operand types (e.g. glc/glc_flat, etc). Introduce parseAMDGPUOperand which can parse any optional operand. DPP and Clamp/OMod have custom handling for now. Sam also suggested to have class hierarchy for operand types instead of table. This can be done in separate change. Remove parseVOP3OptionalOps, parseDS*OptionalOps, parseFlatOptionalOps, parseMubufOptionalOps, parseDPPOptionalOps. Reduce number of definitions of AsmOperand's and MatchClasses' by using common base class. Rename AsmMatcher/InstPrinter methods accordingly. Print immediate type when printing parsed immediate operand. Use 'off' if offset/index register is unused instead of skipping it to make it more readable (also agreed with SP3). Update tests. Reviewers: tstellarAMD, SamWot, artem.tamazov Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19584 llvm-svn: 268015
* [InstCombine][SSE] Regenerated x86 pshufb testsSimon Pilgrim2016-04-291-90/+113
| | | | llvm-svn: 268014
* [mips][microMIPS] Fix offsets for LLE, LWE, SBE, SCE and SHE instructionsZlatko Buljan2016-04-296-7/+122
| | | | | | Differential Revision: http://reviews.llvm.org/D18645 llvm-svn: 268012
* [DeadArgumentElimination] Propagate operand bundles to promoted call sitesDavid Majnemer2016-04-291-0/+29
| | | | | | | We neglected to transfer operand bundles when performing argument promotion. llvm-svn: 268008
* [LoopDist] Add missing RUN line in test from r268006Adam Nemet2016-04-291-0/+2
| | | | llvm-svn: 268007
* [LoopDist] Also emit optimization remark on success (-Rpass=)Adam Nemet2016-04-291-0/+56
| | | | | | | The option -Rpass=loop-distribute now reports the loops that were distributed. llvm-svn: 268006
* [SLPVectorizer] Add operand bundles to vectorized functionsDavid Majnemer2016-04-291-0/+48
| | | | | | | SLPVectorizing a call site should result in further propagation of its bundles. llvm-svn: 268004
* [LoopVectorize] Add operand bundles to vectorized functionsDavid Majnemer2016-04-291-0/+45
| | | | | | | Also, do not crash when calculating a cost model for loop-invariant token values. llvm-svn: 268003
* AMDGPU: Stop reporting an addressing mode for unknown addrspaceMatt Arsenault2016-04-291-4/+20
| | | | | | | | | This was being treated the same as private, which has an immediate offset. For unknown, it probably means it's for a computation not actually being used for accessing memory, so it should not have a nontrivial addressing mode. llvm-svn: 268002
* DivergenceAnalysis: Fix crash with unreachable blocksMatt Arsenault2016-04-291-0/+17
| | | | | | | Unreachable blocks may not be in the dominator tree, so don't crash on them. llvm-svn: 268001
* [ArgumentPromotion] Propagate operand bundles to promoted call sitesDavid Majnemer2016-04-291-0/+31
| | | | | | | | | We neglected to transfer operand bundles when performing argument promotion. This fixes PR27568. llvm-svn: 267986
* [PR25281] Remove AAResultsWrapper from preserved analyses of loop vectorizer.Michael Zolotukhin2016-04-291-0/+59
| | | | | | | We don't preserve AAResults, because, for one, we don't preserve SCEV-AA. That fixes PR25281. llvm-svn: 267980
* RegisterPressure: Fix default lanemask for missing regunit intervalsMatthias Braun2016-04-292-4/+4
| | | | | | | | | | | | | | In case of missing live intervals for a physical registers getLanesWithProperty() would report 0 which was not a safe default in all situations. Add a parameter to pass in a safe default. No testcase because in-tree targets do not skip computing register unit live intervals. Also cleanup the getXXX() functions to not perform the RequireLiveIntervals checks anymore so we do not even need to return safe defaults. llvm-svn: 267977
* [llvm-cov] Don't emit 'nan%' in reportsVedant Kumar2016-04-291-2/+4
| | | | llvm-svn: 267971
* [LoopVectorize] Keep hints from original loop on the vector loopHal Finkel2016-04-291-0/+30
| | | | | | | | | | | | | | | | We need to keep loop hints from the original loop on the new vector loop. Failure to do this meant that, for example: void foo(int *b) { #pragma clang loop unroll(disable) for (int i = 0; i < 16; ++i) b[i] = 1; } this loop would be unrolled. Why? Because we'd vectorize it, thus dropping the hints that unrolling should be disabled, and then we'd unroll it. llvm-svn: 267970
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