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authorTom Stellard <thomas.stellard@amd.com>2016-04-30 04:04:48 +0000
committerTom Stellard <thomas.stellard@amd.com>2016-04-30 04:04:48 +0000
commitc51e4468b7948545b0eb3db3384c88d6ec241eca (patch)
tree14d8acf047e1382706abf43c9d140c42f0b47c67 /llvm/test
parent53ca3c93dba54ce83bc5df5400aaa07cdbaeff1c (diff)
downloadbcm5719-llvm-c51e4468b7948545b0eb3db3384c88d6ec241eca.tar.gz
bcm5719-llvm-c51e4468b7948545b0eb3db3384c88d6ec241eca.zip
AMDGPU/SI: Remove wait state handling for SMRD in SIInsertWaits
This was supposed to be part of r268143. llvm-svn: 268154
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/AMDGPU/missing-store.ll3
-rw-r--r--llvm/test/CodeGen/AMDGPU/salu-to-valu.ll3
2 files changed, 4 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/missing-store.ll b/llvm/test/CodeGen/AMDGPU/missing-store.ll
index 658666304f6..d608fd14ccf 100644
--- a/llvm/test/CodeGen/AMDGPU/missing-store.ll
+++ b/llvm/test/CodeGen/AMDGPU/missing-store.ll
@@ -10,7 +10,8 @@
; SI: buffer_store_dword
; SI: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
; SI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
-; SI-NEXT: s_nop
+; SI: s_load_dword
+; SI: s_nop 2
; SI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}
; SI: buffer_store_dword
; SI: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll b/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
index bcd20ff5bdb..7d167e5dd44 100644
--- a/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
+++ b/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
@@ -56,7 +56,8 @@ done: ; preds = %loop
; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x2ee0
; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
-; SI-NEXT: s_nop
+; SI: s_mov_b32
+; SI: s_nop 2
; SI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, [[OFFSET]]
; CI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xbb8
; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]]
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