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* Add VS2012-generated test inputs for ↵Timur Iskhodzhanov2014-10-136-4/+14
| | | | | | test/tools/llvm-readobj/codeview-linetables.test llvm-svn: 219621
* Fix a broadcast related regression on the vector shuffle lowering.Filipe Cabecinhas2014-10-132-0/+52
| | | | | | | | | | | | Summary: Test by Robert Lougher! Reviewers: chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5745 llvm-svn: 219617
* Adds support for the Cortex-A17 to the ARM backendRenato Golin2014-10-131-0/+32
| | | | | | Patch by Matthew Wahab. llvm-svn: 219606
* [mips] Mark redundant instructions with a comment in ↵Daniel Sanders2014-10-131-2/+9
| | | | | | test/CodeGen/Mips/Fast-ISel/icmpa.ll. llvm-svn: 219605
* [AArch64] Add workaround for Cortex-A53 erratum (835769)Bradley Smith2014-10-131-0/+525
| | | | | | | | | | | | | | | | | | | | Some early revisions of the Cortex-A53 have an erratum (835769) whereby it is possible for a 64-bit multiply-accumulate instruction in AArch64 state to generate an incorrect result. The details are quite complex and hard to determine statically, since branches in the code may exist in some circumstances, but all cases end with a memory (load, store, or prefetch) instruction followed immediately by the multiply-accumulate operation. The safest work-around for this issue is to make the compiler avoid emitting multiply-accumulate instructions immediately after memory instructions and the simplest way to do this is to insert a NOP. This patch implements such work-around in the backend, enabled via the option -aarch64-fix-cortex-a53-835769. The work-around code generation is not enabled by default. llvm-svn: 219603
* [asan-asm-instrumentation] Fixed memory references which includes %rsp as a ↵Yuri Gorshenin2014-10-131-0/+45
| | | | | | | | | | | | | | base or an index register. Summary: [asan-asm-instrumentation] Fixed memory references which includes %rsp as a base or an index register. Reviewers: eugenis Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5599 llvm-svn: 219602
* Revert r219584, "[X86] Memory folding for commutative instructions."NAKAMURA Takumi2014-10-131-16/+0
| | | | | | It broke i686 selfhosting. llvm-svn: 219595
* Revert r219223, it creates invalid PHI nodes.Joerg Sonnenberger2014-10-123-79/+3
| | | | llvm-svn: 219587
* InstCombine: Turn (x != 0 & x <u C) into the canonical range check form (x-1 ↵Benjamin Kramer2014-10-121-0/+11
| | | | | | <u C-1) llvm-svn: 219585
* [X86] Memory folding for commutative instructions.Simon Pilgrim2014-10-121-0/+16
| | | | | | | | | | This patch improves support for commutative instructions in the x86 memory folding implementation by attempting to fold a commuted version of the instruction if the original folding fails - if that folding fails as well the instruction is 're-commuted' back to its original order before returning. This mainly helps the stack inliner better fold reloads of 3 (or more) operand instructions (VEX encoded SSE etc.) but by performing this in the lowest foldMemoryOperandImpl implementation it also replaces the X86InstrInfo::optimizeLoadInstr version and is now used by FastISel too. Differential Revision: http://reviews.llvm.org/D5701 llvm-svn: 219584
* llvm/test/CodeGen: Some tests don't REQUIRE asserts any more. Remove them.NAKAMURA Takumi2014-10-128-8/+0
| | | | llvm-svn: 219581
* Suppress llvm-ar's MRI tests for now on win32, since line_iterator is ↵NAKAMURA Takumi2014-10-113-0/+9
| | | | | | incompatible to CRLF. llvm-svn: 219579
* InstCombine: Don't fold (X <<s log(INT_MIN)) /s INT_MIN to XDavid Majnemer2014-10-111-0/+17
| | | | | | | | | | Consider the case where X is 2. (2 <<s 31)/s-2147483648 is zero but we would fold to X. Note that this is valid when we are in the unsigned domain because we require NUW: 2 <<u 31 results in poison. This fixes PR21245. llvm-svn: 219568
* InstCombine, InstSimplify: (%X /s C1) /s C2 isn't always 0 when C1 * C2 overflowDavid Majnemer2014-10-112-14/+16
| | | | | | | | | | | | | | | | | | consider: C1 = INT_MIN C2 = -1 C1 * C2 overflows without a doubt but consider the following: %x = i32 INT_MIN This means that (%X /s C1) is 1 and (%X /s C1) /s C2 is -1. N. B. Move the unsigned version of this transform to InstSimplify, it doesn't create any new instructions. This fixes PR21243. llvm-svn: 219567
* InstCombine: mul to shl shouldn't preserve nswDavid Majnemer2014-10-114-12/+12
| | | | | | | | | | | | | | | | | consider: mul i32 nsw %x, -2147483648 this instruction will not result in poison if %x is 1 however, if we transform this into: shl i32 nsw %x, 31 then we will be generating poison because we just shifted into the sign bit. This fixes PR21242. llvm-svn: 219566
* Add basic conditional branches in mips fast-iselReed Kotler2014-10-111-0/+34
| | | | | | | | | | | | | | | | | | Summary: Implement the most basic form of conditional branches in Mips fast-isel. Test Plan: br1.ll run 4 flavors of test-suite. mips32 r1/r2 and at -O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D5583 llvm-svn: 219556
* Return undef on FP <-> Int conversions that overflow (PR21330).Sanjay Patel2014-10-101-0/+34
| | | | | | | | | | | | | | | | | | | | The LLVM Lang Ref states for signed/unsigned int to float conversions: "If the value cannot fit in the floating point value, the results are undefined." And for FP to signed/unsigned int: "If the value cannot fit in ty2, the results are undefined." This matches the C definitions. The existing behavior pins to infinity or a max int value, but that may just lead to more confusion as seen in: http://llvm.org/bugs/show_bug.cgi?id=21130 Returning undef will hopefully lead to a less silent failure. Differential Revision: http://reviews.llvm.org/D5603 llvm-svn: 219542
* R600/SI: Change how DS offsets are printedMatt Arsenault2014-10-1016-209/+213
| | | | | | | Match SC by using offset/offset0/offset1 and printing in decimal. llvm-svn: 219537
* R600/SI: Match read2/write2 stride 64 versionsMatt Arsenault2014-10-105-9/+399
| | | | llvm-svn: 219536
* R600/SI: Add load / store machine optimizer pass.Matt Arsenault2014-10-103-6/+843
| | | | | | | | | | | | | Currently this only functions to match simple cases where ds_read2_* / ds_write2_* instructions can be used. In the future it might match some of the other weird load patterns, such as direct to LDS loads. Currently enabled only with a subtarget feature to enable easier testing. llvm-svn: 219533
* This patch teaches ScalarEvolution to pick and use !range metadata.Sanjoy Das2014-10-102-0/+74
| | | | | | | | | | | | It also makes it more aggressive in querying range information by adding a call to isKnownPredicateWithRanges to isLoopBackedgeGuardedByCond and isLoopEntryGuardedByCond. phabricator: http://reviews.llvm.org/D5638 Reviewed by: atrick, hfinkel llvm-svn: 219532
* Implement floating point compare for mips fast-iselReed Kotler2014-10-101-0/+254
| | | | | | | | | | | | | | | | | | Summary: Expand SelectCmp to handle floating point compare Test Plan: fpcmpa.ll run 4 flavors of test-suite, mips32 r1/r2 O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D5567 llvm-svn: 219530
* llvm-ar: Start adding support for mri scripts.Rafael Espindola2014-10-105-0/+25
| | | | | | | | | | | | | | | | | | | | | | I was quiet surprised to find this feature being used. Fortunately the uses I found look fairly simple. In fact, they are just a very verbose version of the regular ar commands. Start implementing it then by parsing the script and setting the command variables as if we had a regular command line. This patch adds just enough support to create an empty archive and do a bit of error checking. In followup patches I will implement at least addmod and addlib. From the description in the manual, even the more general case should not be too hard to implement if needed. The features that don't map 1:1 to the simple command line are * Reading from multiple archives. * Creating multiple archives. llvm-svn: 219521
* implement integer compare in mips fast-iselReed Kotler2014-10-101-0/+203
| | | | | | | | | | | | | | | | | | Summary: implement SelectCmp (integer compare ) in mips fast-isel Test Plan: icmpa.ll also ran 4 test-suite flavors mips32 r1/r2 O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler, mcrosier Differential Revision: http://reviews.llvm.org/D5566 llvm-svn: 219518
* This patch de-pessimizes the calculation of loop trip counts inMark Heffernan2014-10-102-11/+8
| | | | | | | | | | | | | | | | | | | | | ScalarEvolution in the presence of multiple exits. Previously all loops exits had to have identical counts for a loop trip count to be considered computable. This pessimization was implemented by calling getBackedgeTakenCount(L) rather than getExitCount(L, ExitingBlock) inside of ScalarEvolution::getSmallConstantTripCount() (see the FIXME in the comments of that function). The pessimization was added to fix a corner case involving undefined behavior (pr/16130). This patch more precisely handles the undefined behavior case allowing the pessimization to be removed. ControlsExit replaces IsSubExpr to more precisely track the case where undefined behavior is expected to occur. Because undefined behavior is tracked more precisely we can remove MustExit from ExitLimit. MustExit was used to track the case where the limit was computed potentially assuming undefined behavior even if undefined behavior didn't necessarily occur. llvm-svn: 219517
* [MiSched] Fix a logic error in tryPressure()Hal Finkel2014-10-102-3/+5
| | | | | | | | | | | | | Fixes a logic error in the MachineScheduler found by Steve Montgomery (and confirmed by Andy). This has gone unfixed for months because the fix has been found to introduce some small performance regressions. However, Andy has recommended that, at this point, we fix this to avoid further dependence on the incorrect behavior (and then follow-up separately on any regressions), and I agree. Fixes PR18883. llvm-svn: 219512
* Implement floating point to integer conversion in mips fast-iselReed Kotler2014-10-101-0/+35
| | | | | | | | | | | | | | | | | | Summary: Add the ability to convert 64 or 32 bit floating point values to integer in mips fast-isel Test Plan: fpintconv.ll ran 4 flavors of test-suite with no errors, misp32 r1/r2 O0/O2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, rfuhler, mcrosier Differential Revision: http://reviews.llvm.org/D5562 llvm-svn: 219511
* [dwarfdump] Prettyprint DW_AT_APPLE_property_attribute bitfield values.Frederic Riss2014-10-103-0/+56
| | | | | | | | | | | | | This change depends on the ApplePropertyString helper that I sent spearately. Not sure how you want this tested: as a tool test by adding a binary to dump, or as an llvm test starting from an IR file? Reviewers: dblaikie, samsonov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5689 llvm-svn: 219507
* [dwarfdump] Resolve also variable specifications/abstract_origins.Frederic Riss2014-10-108-43/+43
| | | | | | | | | | | | | | | | | DW_AT_specification and DW_AT_abstract_origin resolving was only performed on subroutine DIEs because it used the getSubroutineName method. Introduce a more generic getName() and use it to dump the reference attributes. Testcases have been updated to check the printed names instead of the offsets except when the name could be ambiguous. Reviewers: dblaikie, samsonov Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5625 llvm-svn: 219506
* [mips][microMIPS] Implement ADDIUSP instructionZoran Jovanovic2014-10-102-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D5084 llvm-svn: 219500
* [mips][microMIPS] Implement JR16 instructionZoran Jovanovic2014-10-101-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5062 llvm-svn: 219498
* [mips][microMIPS] Implement ADDIUS5 instructionZoran Jovanovic2014-10-102-0/+7
| | | | | | Differential Revision: http://reviews.llvm.org/D5049 llvm-svn: 219495
* ps][microMIPS] Implement JRC instructionZoran Jovanovic2014-10-101-2/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5045 llvm-svn: 219494
* [mips][microMIPS] Implement JALRS16 instructionZoran Jovanovic2014-10-101-0/+5
| | | | | | Differential Revision: http://reviews.llvm.org/D5027 llvm-svn: 219493
* Add tests for r219479.David Majnemer2014-10-102-0/+263
| | | | llvm-svn: 219480
* SimplifyCFG: Don't convert phis into selects if we could remove undef behaviorArnold Schwaighofer2014-10-101-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instead We used to transform this: define void @test6(i1 %cond, i8* %ptr) { entry: br i1 %cond, label %bb1, label %bb2 bb1: br label %bb2 bb2: %ptr.2 = phi i8* [ %ptr, %entry ], [ null, %bb1 ] store i8 2, i8* %ptr.2, align 8 ret void } into this: define void @test6(i1 %cond, i8* %ptr) { %ptr.2 = select i1 %cond, i8* null, i8* %ptr store i8 2, i8* %ptr.2, align 8 ret void } because the simplifycfg transformation into selects would happen to happen before the simplifycfg transformation that removes unreachable control flow (We have 'unreachable control flow' due to the store to null which is undefined behavior). The existing transformation that removes unreachable control flow in simplifycfg is: /// If BB has an incoming value that will always trigger undefined behavior /// (eg. null pointer dereference), remove the branch leading here. static bool removeUndefIntroducingPredecessor(BasicBlock *BB) Now we generate: define void @test6(i1 %cond, i8* %ptr) { store i8 2, i8* %ptr.2, align 8 ret void } I did not see any impact on the test-suite + externals. rdar://18596215 llvm-svn: 219462
* obj2yaml, COFF: Handle long section namesDavid Majnemer2014-10-102-0/+14
| | | | | | | | | | | | | Long section names are represented as a slash followed by a numeric ASCII string. This number is an offset into a string table. Print the appropriate entry in the string table instead of the less enlightening /4. N.B. yaml2obj already does the right thing, this test exercises both sides of the (de-)serialization. llvm-svn: 219458
* Improve sqrt estimate algorithm (fast-math)Sanjay Patel2014-10-091-9/+2
| | | | | | | | | | | | | | | | | | | This patch changes the fast-math implementation for calculating sqrt(x) from: y = 1 / (1 / sqrt(x)) to: y = x * (1 / sqrt(x)) This has 2 benefits: less code / faster code and one less estimate instruction that may lose precision. The only target that will be affected (until http://reviews.llvm.org/D5658 is approved) is PPC. The difference in codegen for PPC is 2 less flops for a single-precision sqrtf or vector sqrtf and 4 less flops for a double-precision sqrt. We also eliminate a constant load and extra register usage. Differential Revision: http://reviews.llvm.org/D5682 llvm-svn: 219445
* Fix bug in GPR to FPR moves in PPC64LE.Samuel Antao2014-10-091-0/+121
| | | | | | The current implementation of GPR->FPR register moves uses a stack slot. This mechanism writes a double word and reads a word. In big-endian the load address must be displaced by 4-bytes in order to get the right value. In little endian this is no longer required. This patch fixes the issue and adds LE regression tests to fast-isel-conversion which currently expose this problem. llvm-svn: 219441
* [Reassociate] Don't canonicalize X - undef to X + (-undef).Chad Rosier2014-10-091-0/+21
| | | | | | | Phabricator Revision: http://reviews.llvm.org/D5674 PR21205 llvm-svn: 219434
* Revert "[BasicAA] Revert "Revert r218714 - Make better use of zext and sign ↵Hal Finkel2014-10-092-88/+0
| | | | | | | | information."" This reverts commit r219135 -- still causing miscompiles in SPEC it seems... llvm-svn: 219432
* R600/SI: Legalize CopyToReg during instruction selectionTom Stellard2014-10-091-0/+26
| | | | | | | The instruction emitter will crash if it encounters a CopyToReg node with a non-register operand like FrameIndex. llvm-svn: 219428
* R600/SI: Legalize INSERT_SUBREG instructions during PostISelFoldingTom Stellard2014-10-091-0/+15
| | | | | | | | LLVM assumes INSERT_SUBREG will always have register operands, so we need to legalize non-register operands, like FrameIndexes, to avoid random assertion failures. llvm-svn: 219420
* [PPC64] VSX indexed-form loads use wrong instruction formatBill Schmidt2014-10-091-21/+21
| | | | | | | | | | | | | | | | | | The VSX instruction definitions for lxsdx, lxvd2x, lxvdsx, and lxvw4x incorrectly use the XForm_1 instruction format, rather than the XX1Form instruction format. This is likely a pasto when creating these instructions, which were based on lvx and so forth. This patch uses the correct format. The existing reformatting test (test/MC/PowerPC/vsx.s) missed this because the two formats differ only in that XX1Form has an extension to the target register field in bit 31. The tests for these instructions used a target register of 7, so the default of 0 in bit 31 for XForm_1 didn't expose a problem. For register numbers 32-63 this would be noticeable. I've changed the test to use higher register numbers to verify my change is effective. llvm-svn: 219416
* [InstCombine] Fix wrong folding of constant comparisons involving ashr and ↵Andrea Di Biagio2014-10-091-0/+8
| | | | | | | | | | | | | | negative values. This patch fixes a bug in method InstCombiner::FoldCmpCstShrCst where we wrongly computed the distance between the highest bits set of two negative values. This fixes PR21222. Differential Revision: http://reviews.llvm.org/D5700 llvm-svn: 219406
* [AVX512] Extended avx512_binop_rm for AVX512VL subsets.Robert Khasanov2014-10-091-1/+2353
| | | | | | | Added avx512_binop_rm_vl multiclass for VL subset Added encoding tests llvm-svn: 219390
* [AVX512] Intrinsics for vextract*x4Adam Nemet2014-10-081-0/+36
| | | | | | | | This adds the Pat<>'s for the intrinsics. These are necessary because we don't lower these intrinsics to SDNodes but match them directly. See the rational in the previous commit. llvm-svn: 219362
* [AVX512] Add asm-only support for vextract*x4 masking variantsAdam Nemet2014-10-081-0/+8
| | | | | | | | | | | | | | | | These derive from the new asm-only masking definitions. Unfortunately I wasn't able to find a ISel pattern that we could legally generate for the masking variants. The problem is that since the destination is v4* we would need VK4 register classes and v4i1 value types to express the masking. These are however not legal types/classes in AVX512f but only in VL, so things get complicated pretty quickly. We can revisit this question later if we have a more pressing need to express something like this. So the ISel patterns are empty for the masking instructions and the next patch will add Pat<>s instead to match the intrinsics calls with instructions. llvm-svn: 219361
* [X86] Don't transform atomic-load-add into an inc/dec when inc/dec is slowRobin Morisset2014-10-081-0/+17
| | | | llvm-svn: 219357
* [X86] Avoid generating inc/dec when slow for x.atomic_store(1 + x.atomic_load())Robin Morisset2014-10-081-0/+23
| | | | | | | | | | | | | | | | | Summary: I had forgotten to check for NotSlowIncDec in the patterns that can generate inc/dec for the above pattern (added in D4796). This currently applies to Atom Silvermont, KNL and SKX. Test Plan: New checks on atomic_mi.ll Reviewers: jfb, nadav Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5677 llvm-svn: 219336
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