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* [mips] Fix crash on recursive using of .setSimon Atanasyan2019-03-191-0/+5
| | | | | | | | | | | | | Switch to the `MCParserUtils::parseAssignmentExpression` for parsing assignment expressions in the `.set` directive reduces code and allows to print an error message instead of crashing in case of incorrect recursive using of the `.set`. Fix for the bug https://bugs.llvm.org/show_bug.cgi?id=41053. Differential Revision: http://reviews.llvm.org/D59452 llvm-svn: 356461
* [mips] Map SW instruction to its microMIPS R6 variantSimon Atanasyan2019-03-131-2/+22
| | | | | | | | | | | | | | | | To provide mapping between standard and microMIPS R6 variants of the `sw` command we have to rename SWSP_xxx commands from "sw" to "swsp". Otherwise `tablegen` starts to show the error `Multiple matches found for `SW'`. After that to restore printing SWSP command as `sw`, I add an appropriate `MipsInstAlias` instance. We also need to implement "size reduction" for microMIPS R6. But this task is for separate patch. After that the `micromips-lwsp-swsp.ll` test case will be extended. Differential Revision: http://reviews.llvm.org/D59046 llvm-svn: 356045
* [llvm-objdump] - Implement -z/--disassemble-zeroes.George Rimar2019-01-102-4/+4
| | | | | | | | | | | | | | This is https://bugs.llvm.org/show_bug.cgi?id=37151, GNU objdump spec says that "Normally the disassembly output will skip blocks of zeroes.", but currently, llvm-objdump prints them. The patch implements the -z/--disassemble-zeroes option and switches the default to always skip blocks of zeroes. Differential revision: https://reviews.llvm.org/D56083 llvm-svn: 350823
* [mips][micrompis] Emit 16bit NOPs by defaultAleksandar Beserminji2019-01-095-36/+29
| | | | | | | | | Emit 16bit NOPs by default. Use 32bit NOPs in delay slots where necessary. Differential https://reviews.llvm.org/D55323 llvm-svn: 350733
* [mips] Show an error on attempt to use 64-bit PC-relative relocationSimon Atanasyan2018-12-291-0/+2
| | | | | | | | | | | | The following code requests 64-bit PC-relative relocations unsupported by MIPS ABI. Now it triggers an assertion. It's better to show an error message. ``` foo: .quad bar - foo ``` llvm-svn: 350152
* [mips] Show a regular error message on attempt to use one byte relocationSimon Atanasyan2018-12-291-4/+4
| | | | llvm-svn: 350151
* [mips] Fix test typo in rL348914Fangrui Song2018-12-151-1/+1
| | | | | | RUN; -> RUN: llvm-svn: 349258
* [mips] Use llvm-mc -triple option instead of combination of ↵Simon Atanasyan2018-12-1229-122/+142
| | | | | | arch,target-abi,mcpu. NFC llvm-svn: 348914
* [mips][mc] Emit R_{MICRO}MIPS_JALR when expanding jal to jalrVladimir Stefanovic2018-12-101-12/+52
| | | | | | | | | | | When replacing jal with jalr, also emit '.reloc R_MIPS_JALR' (R_MICROMIPS_JALR for micromips). The linker might then be able to turn jalr into a direct call. Add '-mips-jalr-reloc' to enable/disable this feature (default is true). Differential revision: https://reviews.llvm.org/D55292 llvm-svn: 348760
* Reland test/MC/Mips/reloc-directive-label-offset.sVladimir Stefanovic2018-11-221-0/+75
| | | | | | | | | | The test was reverted because it failed on llvm-clang-x86_64-expensive-checks-win builder, and that was because -DEXPENSIVE_CHECKS adds randomness to llvm::sort(), affecting the order of relocation table entries. Modified the test to not have two relocations at the same offset. llvm-svn: 347476
* Removing test/MC/Mips/reloc-directive-label-offset.s temporarilyVladimir Stefanovic2018-11-211-74/+0
| | | | | | | This test is failing on llvm-clang-x86_64-expensive-checks-win builder. Removing it until I get it fixed. llvm-svn: 347433
* [mips][mc] Add basic support for R_MIPS_JALR/R_MICROMIPS_JALRVladimir Stefanovic2018-11-211-0/+13
| | | | | | | | | R_MIPS_JALR/R_MICROMIPS_JALR can now be parsed in .s files and emitted to .o. They are still not generated with JALR. Differential revision: https://reviews.llvm.org/D54721 llvm-svn: 347398
* [MC] Support labels as offsets in .reloc directiveVladimir Stefanovic2018-11-214-9/+93
| | | | | | | | | | | | | | | | | Currently, expressions like .reloc 1f, R_MIPS_JALR, foo 1: nop are not allowed, ie. an offset in .reloc can only be absolute value. This patch adds support for labels as offsets. If offset is a forward declared label, MCObjectStreamer keeps the fixup locally and adds it to the fixups vector after the label (and its offset) is defined. label+number is not supported yet. Differential revision: https://reviews.llvm.org/D53990 llvm-svn: 347397
* [mips] Support sigrie instructionSimon Atanasyan2018-11-063-0/+12
| | | | | | | | | The `sigrie` instruction signals a Reserved Instruction Exception. This patch adds support for assembling / disassembling the instruction. Differential Revision: http://reviews.llvm.org/D53861 llvm-svn: 346230
* [mips] Fix FDE/CFI encoding in case of N32 ABISimon Atanasyan2018-10-091-0/+23
| | | | | | | | | | For O32 and N32 ABI FDE/CFI encoding should be `DW_EH_PE_sdata4` and only N64 ABI uses `DW_EH_PE_sdata8`. To cover all cases this patch check code pointer size and setup a correct FDE/CFI encoding type. Differential revision: https://reviews.llvm.org/D52876 llvm-svn: 344040
* [mips] Set pointer size to 4 bytes for N32 ABISimon Atanasyan2018-10-091-0/+13
| | | | | | | | | | | | | | CodePointerSize and CalleeSaveStackSlotSize values are used in DWARF generation. In case of MIPS it's incorrect to check for Triple::isMIPS64() only this function returns true for N32 ABI too. Now we do not have a method to recognize N32 if it's specified by a command line option and is not a part of a target triple. So we check for Triple::GNUABIN32 only. It's better than nothing. Differential revision: https://reviews.llvm.org/D52874 llvm-svn: 344039
* [mips] Fix MIPS N32 ABI triples supportSimon Atanasyan2018-09-171-0/+4
| | | | | | | | | | | | Add support mips64(el)-linux-gnuabin32 triples, and set them to N32. Debian architecture name mipsn32/mipsn32el are also added. Set UseIntegratedAssembler for N32 if we can detect it. Patch by YunQiang Su. Differential revision: https://reviews.llvm.org/D51408 llvm-svn: 342416
* [mips] Enable the mnemonic spell correctorSimon Atanasyan2018-09-131-0/+65
| | | | | | | | | | | | This implements suggesting alternative mnemonics when an invalid one is specified. For example `addru $9, $6, 17767` leads to the following error message: error: unknown instruction, did you mean: add, addiu, addu, maddu? Differential revision: https://reviews.llvm.org/D40646 llvm-svn: 342119
* [mips] Add missing instructionsAleksandar Beserminji2018-08-2915-38/+50
| | | | | | | | Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920
* [mips] Replace custom parsing logic for data directives by the ↵Simon Atanasyan2018-07-251-1/+45
| | | | | | | | | | | | | | | | | | | | | `addAliasForDirective` The target independent AsmParser doesn't recognise .hword, .word, .dword which are required for Mips. Currently MipsAsmParser recognises these through dispatch to MipsAsmParser::parseDataDirective. This contains equivalent logic to AsmParser::parseDirectiveValue. This patch allows reuse of AsmParser::parseDirectiveValue by making use of addAliasForDirective to support .hword, .word and .dword. Original patch provided by Alex Bradbury at D47001 was modified to fix handling of microMIPS symbols. The `AsmParser::parseDirectiveValue` calls either `EmitIntValue` or `EmitValue`. In this patch we override `EmitIntValue` in the `MipsELFStreamer` to clear a pending set of microMIPS symbols. Differential revision: https://reviews.llvm.org/D49539 llvm-svn: 337893
* [mips] Addition of the [d]rem and [d]remu instructionsStefan Maksimovic2018-07-095-3/+737
| | | | | | | | | | | | | Related to http://reviews.llvm.org/D15772 Depends on http://reviews.llvm.org/D16889 Adds [D]REM[U] instructions. Patch By: Srdjan Obucina Contributions from: Simon Dardis Differential Revision: https://reviews.llvm.org/D17036 llvm-svn: 336545
* [mips] Correct predicates for loads, bit manipulation instructions and some ↵Simon Dardis2018-06-208-0/+40
| | | | | | | | | | | | pseudos Additionally, correct the definition of the rdhwr instruction. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48216 llvm-svn: 335162
* [mips] Mark microMIPS64 as being unsupported.Simon Dardis2018-06-193-48/+8
| | | | | | | | | | There are no provided instruction definitions for this architecture. Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D48320 llvm-svn: 335057
* [mips] Fix the predicates of some aliasesSimon Dardis2018-06-191-0/+2
| | | | | | | | | | | Previously, some aliases were marked as not being available for microMIPS32R6, but this was overridden at the top level. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D48321 llvm-svn: 335053
* [mips] Guard some floating point instructions correctlySimon Dardis2018-06-122-1/+35
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47636 llvm-svn: 334491
* [mips] Partially revert r334031Simon Dardis2018-06-061-19/+0
| | | | | | | | The test changes in r334031 give unstable pass/fail results on the llvm-clang-x86_64-expensive-checks-win buildbot. Revert the test changes to turn the bot green. llvm-svn: 334084
* [mips] Fix the predicates for arithmetic operationsSimon Dardis2018-06-051-0/+19
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47635 llvm-svn: 334031
* [mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructionsSimon Atanasyan2018-06-014-27/+175
| | | | | | | | | | | | | | | The `MipsAsmParser::loadImmediate` can load immediates of various sizes into a register. Idea of this change is to use `loadImmediate` in the `MipsAsmParser::expandMemInst` method to load offset into a register and then call required load/store instruction. The patch removes separate `expandLoadInst` and `expandStoreInst` methods and does everything in the `expandMemInst` method to escape code duplication. Differential Revision: https://reviews.llvm.org/D47316 llvm-svn: 333774
* [mips] Extend list of relocations supported by the `.reloc` directiveSimon Atanasyan2018-06-011-12/+173
| | | | | | | Supporting GOT and TLS related relocations by the `.reloc` directive is useful for purpose of testing various tools like a linker, for example. llvm-svn: 333773
* [mips] Guard 'nop' properly and add mips16's nop instructionSimon Dardis2018-06-012-0/+13
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47583 llvm-svn: 333739
* [mips] Guard all short instructions correctly.Simon Dardis2018-05-313-11/+70
| | | | | | | | Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D47533 llvm-svn: 333645
* [mips] Correct the predicates of arithmetic and logic instructions.Simon Dardis2018-05-302-1/+5
| | | | | | | | | | | | As part of this effort, duplicate and correct the predicates of some aliases. Also disable code generation of some short form instructions for FastISel, as it would otherwise reject them. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D47075 llvm-svn: 333530
* [mips] Process numeric register name in the .set assignment directiveSimon Atanasyan2018-05-291-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | Now LLVM assembler cannot process the following code and generates an error. GNU tools support .set assignment directive with numeric register name. ``` .set r4, 4 test.s:1:11: error: invalid token in expression .set r4, $4 ^ ``` This patch teach assembler to handle such directives correctly. Unfortunately a numeric register name cannot be represented as an expression. That's why we have to maintain a separate `StringMap` in the `MipsAsmParser` to keep mapping between aliases names and register numbers. Differential revision: https://reviews.llvm.org/D47464 llvm-svn: 333428
* [mips] Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 / HI16 ↵Simon Atanasyan2018-05-291-1/+33
| | | | | | | | | | | | | relocations Emit R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_LO16 and R_MICROMIPS_GPREL16/R_MICROMIPS_SUB/R_MICROMIPS_HI16 chains of relocations for %lo(%neg(%gp_rel())) and %hi(%neg(%gp_rel())) expressions in case of microMIPS. Differential Revision: http://reviews.llvm.org/D47220 llvm-svn: 333409
* [mips] Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocationsSimon Atanasyan2018-05-291-2/+12
| | | | | | | | | | | Emit R_MICROMIPS_HIGHER / R_MICROMIPS_HIGHEST relocations for %higher() and %highest() expressions in case of microMIPS. These relocations do exactly the same things as R_MIPS_HIGHER / R_MIPS_HIGHEST, but for consistency it's better to write microMIPS variants. Differential Revision: http://reviews.llvm.org/D47219 llvm-svn: 333407
* [mips] Correct the predicates for a number of instructions.Simon Dardis2018-05-295-10/+26
| | | | | | | | | | Previously, their listed predicates were overridden at the scope level. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46947 llvm-svn: 333405
* [mips] Stop parsing a .set assignment if the first argument is not an identifierSimon Atanasyan2018-05-291-0/+10
| | | | | | | | | | | | | | Before this fix the following code triggers two error messages. The second one is at least useless: test.s:1:9: error: expected identifier after .set .set 123, $a0 ^ test-set.s:1:9: error: unexpected token, expected comma .set 123, $a0 ^ llvm-svn: 333402
* [mips] Correct the predicates of the cache and pref instructionsSimon Dardis2018-05-223-0/+6
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46949 llvm-svn: 332970
* [mips] Add microMIPSR6 ll/sc instructions.Simon Dardis2018-05-203-0/+14
| | | | | | | | | | Previously the compiler was using the microMIPSR3 variants, incorrectly. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46948 llvm-svn: 332820
* [mips] Add support for Global INValidate ASEPetar Jovanovic2018-05-177-0/+94
| | | | | | | | | | | | | | | | | | This includes Instructions: ginvi, ginvt, Assembler directives: .set ginv, .set noginv, .module ginv, .module noginv Attribute: ginv .MIPS.abiflags: GINV (0x20000) Patch by Vladimir Stefanovic. Differential Revision: https://reviews.llvm.org/D46268 llvm-svn: 332624
* [mips] Mark select instructions correctlySimon Dardis2018-05-151-2/+10
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46702 llvm-svn: 332364
* [mips] Add disassembly support for comparison instructionsSimon Dardis2018-05-151-0/+160
| | | | llvm-svn: 332340
* [mips] Fix predicates of mfc1, mtc1 instructionsSimon Dardis2018-05-151-0/+8
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46692 llvm-svn: 332339
* [mips] Fix the predicates of round, ceiling, floor and trunc.Simon Dardis2018-05-1415-72/+203
| | | | | | | | Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
* [mips] Add missing test case from r332227Simon Dardis2018-05-141-0/+26
| | | | | | I did not commit this test from D46689. llvm-svn: 332241
* [mips] Correct the predicates of indexed floating point stores and loads.Simon Dardis2018-05-141-6/+0
| | | | | | | | | | Also, fix the register class for microMIPS. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46689 llvm-svn: 332227
* [mips] Enable disassembly of fused (negative) multiply add/sub instructionsSimon Dardis2018-05-111-0/+7
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46392 llvm-svn: 332097
* [mips] Accept 32-bit offsets for ld/sd/lld commandsSimon Atanasyan2018-05-102-6/+38
| | | | | | | | | | | | This is a follow up to the rL330983. The patch teaches ld, sd, and lld commands accept 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. In fact, these commands should accept 64-bit offsets, but so large offsets require another command expanding and will be supported by a separate patch. Differential Revision: https://reviews.llvm.org/D46629 llvm-svn: 331997
* [mips] Accept 32-bit offsets for lh and lhu commandsSimon Atanasyan2018-05-106-16/+52
| | | | | | | | | | This is a follow up to the rL330983. The patch teaches lh and lhu commands accepts 32-bit memory offsets by replacing `mem_simm16` operand to `mem_simmptr`. Differential Revision: https://reviews.llvm.org/D46513 llvm-svn: 331996
* [mips] Correct the predicates of cvt.fmt.fmt instructionsSimon Dardis2018-05-109-72/+152
| | | | | | | | Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46390 llvm-svn: 331969
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