[mips] Correct the predicates for a number of instructions.

Previously, their listed predicates were overridden at the scope level.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46947

llvm-svn: 333405

5 files changed, 26 insertions, 10 deletions

diff --git a/llvm/test/MC/Mips/micromips-16-bit-instructions.s b/llvm/test/MC/Mips/micromips-16-bit-instructions.s
index 25fbfdb92ad..53efb6c152c 100644
--- a/llvm/test/MC/Mips/micromips-16-bit-instructions.s
+++ b/llvm/test/MC/Mips/micromips-16-bit-instructions.s
@@ -40,8 +40,8 @@
 # CHECK-EL: addiusp 1024            # encoding: [0x01,0x4c]
 # CHECK-EL: addiusp 1028            # encoding: [0x03,0x4c]
 # CHECK-EL: addiusp -16             # encoding: [0xf9,0x4f]
-# CHECK-EL: mfhi    $9              # encoding: [0x09,0x46]
-# CHECK-EL: mflo    $9              # encoding: [0x49,0x46]
+# CHECK-EL: mfhi16  $9              # encoding: [0x09,0x46]
+# CHECK-EL: mflo16  $9              # encoding: [0x49,0x46]
 # CHECK-EL: move    $25, $1         # encoding: [0x21,0x0f]
 # CHECK-EL: movep   $5, $6, $2, $3  # encoding: [0x34,0x84]
 # CHECK-EL: jrc     $9              # encoding: [0xa9,0x45]
@@ -95,8 +95,8 @@
 # CHECK-EB: addiusp 1024            # encoding: [0x4c,0x01]
 # CHECK-EB: addiusp 1028            # encoding: [0x4c,0x03]
 # CHECK-EB: addiusp -16             # encoding: [0x4f,0xf9]
-# CHECK-EB: mfhi    $9              # encoding: [0x46,0x09]
-# CHECK-EB: mflo    $9              # encoding: [0x46,0x49]
+# CHECK-EB: mfhi16  $9              # encoding: [0x46,0x09]
+# CHECK-EB: mflo16  $9              # encoding: [0x46,0x49]
 # CHECK-EB: move    $25, $1         # encoding: [0x0f,0x21]
 # CHECK-EB: movep   $5, $6, $2, $3  # encoding: [0x84,0x34]
 # CHECK-EB: jrc     $9              # encoding: [0x45,0xa9]
@@ -148,8 +148,8 @@
     addiusp 1024
     addiusp 1028
     addiusp -16
-    mfhi    $9
-    mflo    $9
+    mfhi16  $9
+    mflo16  $9
     move    $25, $1
     movep   $5, $6, $2, $3
     jrc     $9
diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s
index 86aa41cacad..6fa732d75d2 100644
--- a/llvm/test/MC/Mips/micromips/valid.s
+++ b/llvm/test/MC/Mips/micromips/valid.s
@@ -24,8 +24,8 @@ sb16 $3, 4($16)             # CHECK: sb16 $3, 4($16)    # encoding: [0x89,0x84]
 sh16 $4, 8($17)             # CHECK: sh16 $4, 8($17)    # encoding: [0xaa,0x14]
 sw16 $4, 4($17)             # CHECK: sw16 $4, 4($17)    # encoding: [0xea,0x11]
 sw16 $zero, 4($17)          # CHECK: sw16 $zero, 4($17) # encoding: [0xe8,0x11]
-mfhi $9                     # CHECK: mfhi $9            # encoding: [0x46,0x09]
-mflo $9                     # CHECK: mflo $9            # encoding: [0x46,0x49]
+mfhi16 $9                   # CHECK: mfhi16 $9          # encoding: [0x46,0x09]
+mflo16 $9                   # CHECK: mflo16 $9          # encoding: [0x46,0x49]
 move $25, $1                # CHECK: move $25, $1       # encoding: [0x0f,0x21]
 jrc $9                      # CHECK: jrc $9             # encoding: [0x45,0xa9]
 jalr $9                     # CHECK: jalr $9            # encoding: [0x45,0xc9]
@@ -133,10 +133,10 @@ movt $9, $6, $fcc0          # CHECK: movt $9, $6, $fcc0     # encoding: [0x55,0x
 movf $9, $6, $fcc0          # CHECK: movf $9, $6, $fcc0     # encoding: [0x55,0x26,0x01,0x7b]
 # FIXME: MTHI should also have its 16 bit implementation selected in micromips
 mthi   $6                   # CHECK: mthi   $6              # encoding: [0x00,0x06,0x2d,0x7c]
-mfhi   $6                   # CHECK: mfhi   $6              # encoding: [0x46,0x06]
+mfhi   $6                   # CHECK: mfhi   $6              # encoding: [0x00,0x06,0x0d,0x7c]
 # FIXME: MTLO should also have its 16 bit implementation selected in micromips
 mtlo   $6                   # CHECK: mtlo   $6              # encoding: [0x00,0x06,0x3d,0x7c]
-mflo   $6                   # CHECK: mflo   $6              # encoding: [0x46,0x46]
+mflo   $6                   # CHECK: mflo   $6              # encoding: [0x00,0x06,0x1d,0x7c]
 mfhc1 $4, $f0               # CHECK: mfhc1 $4, $f0          # encoding: [0x54,0x80,0x30,0x3b]
                             # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} MFHC1_D32_MM
 mthc1 $4, $f0               # CHECK: mthc1 $4, $f0          # encoding: [0x54,0x80,0x38,0x3b]
diff --git a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s
index 8bccb4c2b28..0995b71628d 100644
--- a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s
+++ b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s
@@ -28,3 +28,7 @@
   sc $4, -513($5)          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   ll $4, 512($5)           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   ll $4, -513($5)          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  lwr $4, 1($5)            # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  lwl $4, 1($5)            # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  swr $4, 1($5)            # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  swl $4, 1($5)            # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s
index e301ee0cb3a..d194d3bb92e 100644
--- a/llvm/test/MC/Mips/micromips32r6/invalid.s
+++ b/llvm/test/MC/Mips/micromips32r6/invalid.s
@@ -382,3 +382,11 @@
   lwc2 $1, 16($32)         # CHECK: :[[@LINE]]:15: error: invalid register number
   sdc2 $1, 8($32)          # CHECK: :[[@LINE]]:14: error: invalid register number
   swc2 $1, 777($32)        # CHECK: :[[@LINE]]:16: error: invalid register number
+  movn  $3, $3, $4         # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  movz  $3, $3, $4         # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  movt  $4, $5, $fcc0      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  movf  $4, $5, $fcc0      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  madd  $4, $5             # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  maddu $4, $5             # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  msub  $4, $5             # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  msubu $4, $5             # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/micromips32r6/valid.s b/llvm/test/MC/Mips/micromips32r6/valid.s
index e799e90625e..d9f51758bad 100644
--- a/llvm/test/MC/Mips/micromips32r6/valid.s
+++ b/llvm/test/MC/Mips/micromips32r6/valid.s
@@ -117,8 +117,10 @@
                            # CHECK-NEXT:                # <MCInst #{{.*}} PREF_MMR6
   sb16 $3, 4($16)          # CHECK: sb16 $3, 4($16)     # encoding: [0x89,0x84]
   seb $3, $4               # CHECK: seb $3, $4          # encoding: [0x00,0x64,0x2b,0x3c]
+                           # CHECK-NEXT:                # <MCInst #{{.*}} SEB_MM
   seb $3                   # CHECK: seb $3, $3          # encoding: [0x00,0x63,0x2b,0x3c]
   seh $3, $4               # CHECK: seh $3, $4          # encoding: [0x00,0x64,0x3b,0x3c]
+                           # CHECK-NEXT:                # <MCInst #{{.*}} SEH_MM
   seh $3                   # CHECK: seh $3, $3          # encoding: [0x00,0x63,0x3b,0x3c]
   seleqz $2,$3,$4          # CHECK: seleqz $2, $3, $4   # encoding: [0x00,0x83,0x11,0x40]
   selnez $2,$3,$4          # CHECK: selnez $2, $3, $4   # encoding: [0x00,0x83,0x11,0x80]
@@ -363,9 +365,11 @@
   bc2eqzc $31, 8           # CHECK: bc2eqzc $31, 8         # encoding: [0x41,0x5f,0x00,0x04]
   bc2nezc $31, 8           # CHECK: bc2nezc $31, 8         # encoding: [0x41,0x7f,0x00,0x04]
   ins $9, $6, 3, 7         # CHECK: ins $9, $6, 3, 7       # encoding: [0x01,0x26,0x48,0xcc]
+                           # CHECK-NEXT:                   # <MCInst #{{.*}} INS_MMR6
   jalrc $4, $5             # CHECK: jalrc $4, $5           # encoding: [0x00,0x85,0x0f,0x3c]
   jalrc $5                 # CHECK: jalrc $5               # encoding: [0x03,0xe5,0x0f,0x3c]
   ext $9, $6, 3, 7         # CHECK: ext $9, $6, 3, 7       # encoding: [0x01,0x26,0x30,0xec]
+                           # CHECK-NEXT:                   # <MCInst #{{.*}} EXT_MMR6
   bovc $2, $4, 24          # CHECK: bovc $2, $4, 24        # encoding: [0x74,0x44,0x00,0x0c]
   bovc $4, $2, 24          # CHECK: bovc $4, $2, 24        # encoding: [0x74,0x44,0x00,0x0c]
   bnvc $2, $4, 24          # CHECK: bnvc $2, $4, 24        # encoding: [0x7c,0x44,0x00,0x0c]