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* [WebAssembly] Add a comment about why v128.const test was disabled (NFC)Heejin Ahn2019-02-051-0/+2
* [WebAssembly] Disable a v128.const test line temporarilyHeejin Ahn2019-02-051-1/+1
* [WebAssembly] Make disassembler always emit most canonical name.Wouter van Oortmerssen2019-02-051-2/+9
* [X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having two argum...Craig Topper2019-02-042-98/+98
* [X86] Print %st(0) as %st when its implicit to the instruction. Continue prin...Craig Topper2019-02-041-112/+112
* Revert r352985 "[X86] Print %st(0) as %st to match what gcc inline asm uses a...Craig Topper2019-02-042-144/+144
* [X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber na...Craig Topper2019-02-032-144/+144
* [AMDGPU][MC][GFX8+][DISASSEMBLER] Corrected 1/2pi value for 64-bit operandsDmitry Preobrazhensky2019-01-181-0/+7
* [MSP430] Minor fixes/improvements for assembler/disassemblerAnton Korobeynikov2019-01-101-0/+13
* [MSP430] Add missing instruction formsAnton Korobeynikov2019-01-101-1/+2
* [AArch64] Move feature predctrl to predresDiogo N. Sampaio2019-01-091-2/+2
* [WebAssembly] Massive instruction renamingThomas Lively2019-01-081-2/+2
* [WebAssembly] Fixed disassembler not knowing about new brlist operandWouter van Oortmerssen2019-01-031-0/+4
* [WebAssembly] Made InstPrinter more robustWouter van Oortmerssen2019-01-031-0/+9
* [NFC] Fix missing testfile change of rL350299Diogo N. Sampaio2019-01-031-2/+2
* [ARM] Add command-line option for SBDiogo N. Sampaio2019-01-032-9/+9
* [WebAssembly] made assembler parse block_typeWouter van Oortmerssen2019-01-021-4/+2
* [AArch64] Add command-line option for SBDiogo N. Sampaio2018-12-282-9/+9
* [Sparc] Add membar assembler tagsDaniel Cederman2018-12-131-1/+16
* [AArch64] Add command-line option for SSBSPablo Barrio2018-12-032-10/+13
* [RISCV] Fix test/MC/Disassembler/RISCV/invalid-instruction.txt after rL347988Alex Bradbury2018-12-031-4/+0
* [MSP430] Add MC layerAnton Korobeynikov2018-11-152-0/+30
* [AArch64] Support HiSilicon's TSV110 processorBryan Chan2018-11-091-0/+1
* [WebAssembly] Read prefixed opcodes as ULEB128sThomas Lively2018-11-091-0/+9
* [WebAssembly] Renumber and LEB128-encode SIMD opcodesThomas Lively2018-11-091-2/+2
* Revert "[MSP430] Add MC layer"Davide Italiano2018-11-082-30/+0
* [MSP430] Add MC layerAnton Korobeynikov2018-11-082-0/+30
* [FIX][AArch64] Add support for UDF instructionDiogo N. Sampaio2018-10-301-5/+3
* [FIX][AArch64] Add support for UDF instructionDiogo N. Sampaio2018-10-301-17/+5
* [AArch64] Add support for UDF instructionDiogo N. Sampaio2018-10-301-0/+30
* [RISCV] Fix disassembling of fence instruction with invalid fieldAna Pazos2018-10-111-0/+9
* [X86][Disassembler] Add bizarro versions of the MOVSXD instruction that sign ...Craig Topper2018-10-021-0/+9
* [AArch64][v8.5A] Add Memory Tagging instructionsOliver Stannard2018-10-022-3/+455
* [AArch64][v8.5A] Add Memory Tagging system registersOliver Stannard2018-10-021-2/+42
* [AArch64][v8.5A] Add MTE system instructionsOliver Stannard2018-10-021-0/+60
* [ARM][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-282-4/+4
* [AArch64][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-272-3/+6
* [AArch64][v8.5A] Add Branch Target Identification instructionsOliver Stannard2018-09-271-0/+18
* [AArch64][v8.5A] Add speculation restriction system registersOliver Stannard2018-09-271-0/+52
* [AArch64][v8.5A] Add Armv8.5-A random number instructionsOliver Stannard2018-09-271-0/+12
* [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instructionOliver Stannard2018-09-271-0/+7
* [AArch64][v8.5A] Add prediction invalidation instructions to AArch64Oliver Stannard2018-09-271-0/+15
* [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction setsOliver Stannard2018-09-272-0/+18
* [AArch64][v8.5A] Add speculation barrier to AArch64 instruction setOliver Stannard2018-09-271-0/+9
* [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructionsOliver Stannard2018-09-271-5/+94
* [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlagOliver Stannard2018-09-271-0/+12
* [RISCV] Fix decoding of invalid instruction with C extension enabled.Ana Pazos2018-09-131-0/+13
* [WebAssembly] v8x16.shuffleThomas Lively2018-09-071-0/+3
* [RISCV] Fix crash in decoding instruction with unknown floating point roundin...Ana Pazos2018-09-071-0/+9
* [RISCV] Fix AddressSanitizer heap-buffer-overflow in disassemblingAna Pazos2018-09-072-0/+11
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