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* [PowerPC] Add support for vmsumudmAhsan Saghir2020-06-221-0/+3
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-144-8/+18
* [AMDGPU] Remove duplicate gfx10 assembler and disassembler testsJay Foad2020-01-141-9/+0
* [AMDGPU] Add gfx9 assembler and disassembler test casesJay Foad2020-01-141-0/+1902
* [AMDGPU] Add gfx8 assembler and disassembler test casesJay Foad2020-01-121-0/+3105
* Reverting, broke some bots. Need further investigation.Diogo Sampaio2020-01-104-18/+8
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-104-8/+18
* [AArch64][v8.3a] Don't emit LDRA '[xN]!' alias in disassembly.Simon Tatham2019-11-281-2/+2
* [AMDGPU][MC][GFX10] Enabled v_movrel*[sdwa|dpp|dpp8] opcodesDmitry Preobrazhensky2019-11-183-0/+60
* [AArch64][v8.3a] Add LDRA '[xN]!' alias.Ahmed Bougacha2019-11-131-8/+14
* [PowerPC] Implementing overflow version for XO-Form instructionsStefan Pintile2019-11-112-0/+252
* [mips] Implement Octeon+ `saa` and `saad` instructionsSimon Atanasyan2019-11-072-0/+66
* [AMDGPU] return Fail instead of SolfFail from addOperand()Stanislav Mekhanoshin2019-11-051-0/+4
* [mips] Add disassembler tests for `octeon` CPU. NFCSimon Atanasyan2019-11-042-0/+62
* [mips] Add disassembler tests for `sigrie` instruction. NFCSimon Atanasyan2019-11-044-0/+4
* [AMDGPU][MC][GFX10] Added v_interp_[p1/p2/mov]_f32_e64Dmitry Preobrazhensky2019-10-281-0/+132
* [AMDGPU][MC][GFX10] Added sdwa/dpp versions of v_cndmask_b32Dmitry Preobrazhensky2019-10-182-0/+16
* [AArch64] Adding support for PMMIR_EL1 registerVictor Campos2019-10-181-0/+10
* [AArch64,Assembler] Compiler support for ID_MMFR5_EL1Mark Murray2019-10-161-0/+2
* [WebAssembly] Allow multivalue types in block signature operandsThomas Lively2019-10-151-1/+4
* [AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_[read/write...Dmitry Preobrazhensky2019-10-111-24/+24
* [AMDGPU][MC][GFX6][GFX7][GFX10] Added instructions buffer_atomic_[fcmpswap/fm...Dmitry Preobrazhensky2019-10-111-0/+31
* [AMDGPU][MC][GFX10] Enabled null for 64-bit dst operandsDmitry Preobrazhensky2019-10-111-0/+9
* [AMDGPU][MC][GFX10][WS32] Corrected decoding of dst operand for v_cmp_*_sdwa ...Dmitry Preobrazhensky2019-10-041-0/+6
* [AMDGPU][MC][GFX10] Enabled decoding of 'null' operandDmitry Preobrazhensky2019-10-041-0/+7
* [AMDGPU][MC][GFX10] Corrected definition of FLAT GLOBAL/SCRATCH instructionsDmitry Preobrazhensky2019-10-041-0/+75
* [AArch64InstPrinter] prefer bfi to bfc for < armv8.2-aNick Desaulniers2019-10-031-2/+5
* [MC][ARM] vscclrm disassembles as vldmiaAlexandros Lamprineas2019-09-271-1/+4
* [SystemZ] Support z15 processor nameUlrich Weigand2019-09-201-2/+2
* [mips] Fix decoding of microMIPS JALX instructionSimon Atanasyan2019-09-092-0/+2
* [ARM] Remove some spurious MVE reduction instructions.Simon Tatham2019-09-091-1/+38
* [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodingsOliver Stannard2019-09-091-0/+42
* [ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodingsOliver Stannard2019-09-031-0/+178
* [PowerPC] Support extended mnemonics mffprwz etc.Jinsong Ji2019-08-291-4/+19
* [AArch64] Update MTE system register encodingsLuke Cheeseman2019-08-211-20/+20
* Re-commit: [AMDGPU] Use S_DENORM_MODE for gfx10Austin Kerbow2019-08-061-1/+1
* Revert "Try to fix failing AMDGPU disasm test, both Lin/Win agree this is 0 n...Dmitri Gribenko2019-08-051-1/+1
* Try to fix failing AMDGPU disasm test, both Lin/Win agree this is 0 not 0x0Reid Kleckner2019-08-051-1/+1
* [ARM] Reject CSEL instructions with invalid operandsMikhail Maltsev2019-07-311-13/+12
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-311-0/+19
* [mips] Add (dis)assembler tests for beqzl and bnezl instructions. NFCSimon Atanasyan2019-07-272-0/+4
* [AArch64] Define ETE and TRBE system registersMomchil Velikov2019-07-262-0/+71
* [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1Pablo Barrio2019-07-251-3/+6
* [ARM] Add <saturate> operand to SQRSHRL and UQRSHLLMikhail Maltsev2019-07-191-2/+10
* Revert [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-171-19/+0
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-171-0/+19
* [WebAssembly] Rename except_ref type to exnrefHeejin Ahn2019-07-151-1/+1
* [AMDGPU][MC] Corrected encoding of src0 for DS_GWS_* instructionsDmitry Preobrazhensky2019-07-154-74/+74
* [SystemZ] Add support for new cpu architecture - arch13Ulrich Weigand2019-07-121-0/+1479
* [ARM] Remove nonexistent unsigned forms of MVE VQDMLAH.Simon Tatham2019-07-111-13/+14
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