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| author | Oliver Stannard <oliver.stannard@arm.com> | 2018-10-02 09:54:35 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2018-10-02 09:54:35 +0000 |
| commit | 2a5fcba94b7e19827621361cfd9ce83e30c8d0a8 (patch) | |
| tree | 143367e6483d5985390fbede035d1c5a1d4f9737 /llvm/test/MC/Disassembler | |
| parent | 4493f421acc535e0ca80670b5465ae5a41532a8e (diff) | |
| download | bcm5719-llvm-2a5fcba94b7e19827621361cfd9ce83e30c8d0a8.tar.gz bcm5719-llvm-2a5fcba94b7e19827621361cfd9ce83e30c8d0a8.zip | |
[AArch64][v8.5A] Add Memory Tagging system registers
This adds new system registers introduced by the Memory Tagging
extension.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52488
llvm-svn: 343571
Diffstat (limited to 'llvm/test/MC/Disassembler')
| -rw-r--r-- | llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt | 44 |
1 files changed, 42 insertions, 2 deletions
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt index 1b2cd1814a7..99b90812518 100644 --- a/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt +++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt @@ -1,6 +1,6 @@ -# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s | FileCheck %s # RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NOMTE -# RUN: llvm-mc -triple=aarch64 -mattr=-mte -disassemble < %s | FileCheck %s --check-prefix=NOMTE +# RUN: llvm-mc -triple=aarch64 -mattr=-mte -disassemble < %s | FileCheck %s --check-prefix=NOMTE [0x60,0x76,0x08,0xd5] [0x81,0x76,0x08,0xd5] @@ -58,3 +58,43 @@ # NOMTE: sys #3, c7, c13, #5, x15 # NOMTE: sys #3, c7, c14, #5, x16 # NOMTE: sys #3, c7, c4, #4, x17 + +[0xe0,0x42,0x3b,0xd5] +[0xc1,0x10,0x38,0xd5] +[0xa2,0x10,0x38,0xd5] +[0x03,0x65,0x38,0xd5] +[0x04,0x65,0x3c,0xd5] +[0x05,0x66,0x3e,0xd5] +[0x06,0x66,0x3d,0xd5] +[0x27,0x66,0x38,0xd5] + +# CHECK: mrs x0, TCO +# CHECK: mrs x1, GCR_EL1 +# CHECK: mrs x2, RGSR_EL1 +# CHECK: mrs x3, TFSR_EL1 +# CHECK: mrs x4, TFSR_EL2 +# CHECK: mrs x5, TFSR_EL3 +# CHECK: mrs x6, TFSR_EL12 +# CHECK: mrs x7, TFSRE0_EL1 + +[0x9f,0x40,0x03,0xd5] + +# CHECK: msr TCO, #0 + +[0xe0,0x42,0x1b,0xd5] +[0xc1,0x10,0x18,0xd5] +[0xa2,0x10,0x18,0xd5] +[0x03,0x65,0x18,0xd5] +[0x04,0x65,0x1c,0xd5] +[0x05,0x66,0x1e,0xd5] +[0x06,0x66,0x1d,0xd5] +[0x27,0x66,0x18,0xd5] + +# CHECK: msr TCO, x0 +# CHECK: msr GCR_EL1, x1 +# CHECK: msr RGSR_EL1, x2 +# CHECK: msr TFSR_EL1, x3 +# CHECK: msr TFSR_EL2, x4 +# CHECK: msr TFSR_EL3, x5 +# CHECK: msr TFSR_EL12, x6 +# CHECK: msr TFSRE0_EL1, x7 |
