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* [mips] Add disassembler tests for `sigrie` instruction. NFCSimon Atanasyan2019-11-042-0/+2
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* [mips] Mark the `lwupc` instruction as MIPS64 R6 onlySimon Atanasyan2019-06-192-2/+0
| | | | | | | | | | The "The MIPS64 Instruction Set Reference Manual" [1] states that the `lwupc` is MIPS64 Release 6 only. It should not be supported for 32-bit CPUs. [1] https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf llvm-svn: 363886
* [mips] Correct the predicates for special nops, tlb ctrl instrs, software ↵Simon Dardis2018-04-122-0/+3
| | | | | | | | | | breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
* [mips][microMIPS] add lapc instructionPetar Jovanovic2017-09-112-2/+2
| | | | | | | | | | Implement LAPC instruction for mips32r6, mips64r6 and micromips32r6. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D35984 llvm-svn: 312934
* Reland r306095: [mips] Fix reg positions in the aui/daui instructionsPetar Jovanovic2017-06-232-2/+2
| | | | | | | | | | | | | | | | After fixing (r306173) a failing test in the lld test suite (r306173), reland r306095. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aui/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. llvm-svn: 306174
* Revert r306095: [mips] Fix reg positions in the aui/daui instructionsPetar Jovanovic2017-06-232-2/+2
| | | | | | | | | | | | | | | ELF/mips-plt-r6.s in lld-test is failing. Reverting the change. Original commit message: [mips] Fix register positions in the aui/daui instructions Swapped the position of the rt and rs register in the aut/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. llvm-svn: 306099
* [mips] Fix register positions in the aui/daui instructionsPetar Jovanovic2017-06-232-2/+2
| | | | | | | | | | | | Swapped the position of the rt and rs register in the aut/daui instructions for mips32r6 and mips64r6. With this change, the format of the generated instructions complies with specifications and GCC. Patch by Milos Stojanovic. Differential Revision: https://reviews.llvm.org/D33988 llvm-svn: 306095
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-10-142-2/+2
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 284218
* [mips] Add IAS support for dvp, evpSimon Dardis2016-10-132-0/+8
| | | | | | | | | | | | | These instructions were only defined for microMIPSR6 previously. Add definitions for MIPSR6, correct definitions for microMIPSR6, flag these instructions as having unmodelled side effects (they disable/enable virtual processors) and add missing disassember tests for microMIPSR6. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24291 llvm-svn: 284115
* Recommit: "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-052-0/+8
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
* Revert "[mips] Add rsqrt, recip for MIPS"Simon Dardis2016-10-052-8/+0
| | | | | | | This reverts commit r282485 which contain two patches instead of one. llvm-svn: 283327
* [mips] Add rsqrt, recip for MIPSSimon Dardis2016-09-272-0/+8
| | | | | | | | | | | Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 282485
* Revert "[mips] Fix aui/daui/dahi/dati for MIPSR6"Simon Dardis2016-09-162-2/+2
| | | | | | This reverts r281724. Still need dsanders to accept this. llvm-svn: 281726
* [mips] Fix aui/daui/dahi/dati for MIPSR6Simon Dardis2016-09-162-2/+2
| | | | | | | | | | | | For compatiblity with binutils, define these instructions to take two registers with a 16bit unsigned immediate. Both of the registers have to be same for dahi and dati. Reviewers: vkalintiris, dsanders, zoran.jovanovic Differential Review: https://reviews.llvm.org/D21473 llvm-svn: 281724
* [MIPS][LLVM-MC] Fix Disassemble of Negative OffsetSagar Thakur2016-05-242-58/+86
| | | | | | | | | | | Patch by Nitesh Jain. Summary: The type of Imm in MipsDisassembler.cpp was incorrect since SignExtend64 return int64_t type.As per the MIPSr6 doc ,the offset is added to the address of the instruction following the branch (not the branch itself), to form a PC-relative effective target address hence “4” is added to the offset. The offset of some test case are update to reflect the changes due to “ + 4 ” offset and new test case for negative offset are added. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D17540 llvm-svn: 270542
* Summary:Simon Dardis2016-04-142-0/+4
| | | | | | | | | | Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. This patch was previous committed as r266055 as seemed to have caused some spurious test failures. They did not reappear after further local testing. llvm-svn: 266301
* Revert "[mips] MIPSR6 Compact branch aliases"Simon Dardis2016-04-122-4/+0
| | | | | | | | This reverts commit r266055. ps4-buildslave2 is highlighting a failure. llvm-svn: 266061
* [mips] MIPSR6 Compact branch aliasesSimon Dardis2016-04-122-0/+4
| | | | | | | | | | | | Summary: Alias 'jic $reg, 0' to 'jrc $reg' and 'jialc $reg, 0' to 'jalrc $reg' like binutils. Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D18856 llvm-svn: 266055
* [mips][ias] Range check uimm2 operands and fix a bug this revealed.Daniel Sanders2015-11-062-2/+2
| | | | | | | | | | | | | | | Summary: The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA (unlike the MSA version) failed to account for the off-by-one encoding of the immediate. The range is actually 1..4 rather than 0..3. Reviewers: vkalintiris Subscribers: atanasyan, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14015 llvm-svn: 252295
* [mips] Added support for the ERETNC instruction.Vasileios Kalintiris2015-07-201-0/+1
| | | | | | | | | | | | | | Summary: This required adding the instruction predicate HasMips32r5. Patch by Scott Egerton. Reviewers: dsanders, vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11136 llvm-svn: 242666
* [mips] Fold duplicate big-endian disassembler tests together.Daniel Sanders2015-06-271-0/+23
| | | | llvm-svn: 240887
* [mips] Sort big-endian disassembler tests by opcode.Daniel Sanders2015-06-271-120/+120
| | | | llvm-svn: 240885
* [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.Daniel Sanders2015-06-272-0/+4
| | | | | | | | | | | | | | | | | Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
* [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 ↵Vladimir Medic2015-01-293-3/+4
| | | | | | it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. llvm-svn: 227430
* When disassembler meets compact jump instructions for r6 it crashes as the ↵Vladimir Medic2015-01-263-2/+5
| | | | | | access to operands array is out of range. This patch removes dedicated decoder method that wrongly handles decoding of these instructions. llvm-svn: 227084
* mips: Fix "XPASS" test results by removing 'not' commandsReid Kleckner2015-01-231-1/+1
| | | | | | | | | | | These tests are asserting and crashing for me, and 'not' sees that as a non-zero exit code instead of a signal code for obscure Windows reasons. This causes the test to pass, giving me an unclean 'ninja check'. The test is already XFAILd, so just run the test without 'not' and let lit handle the failure. llvm-svn: 226958
* [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 ↵Vladimir Medic2015-01-213-4/+8
| | | | | | instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. llvm-svn: 226652
* [mips] Make whitespace in disassembler tests more consistent. NFC.Daniel Sanders2015-01-183-296/+296
| | | | | | | | | | The tests for the ISA's should now be approximately diffable. That is, the output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines for instructions that were added/removed to/from MIPS-I by MIPS-II. This doesn't work perfectly at the moment due to ordering differences but it should be close. llvm-svn: 226408
* [mips] Make whitespace of disassembler tests more consistent by removing ↵Daniel Sanders2015-01-183-4/+0
| | | | | | blank lines. NFC. llvm-svn: 226407
* Add disassembler tests for mips32r6 platform. There are no functional changes.Vladimir Medic2015-01-153-0/+307
llvm-svn: 226165
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