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authorVladimir Medic <Vladimir.Medic@imgtec.com>2015-01-29 11:33:41 +0000
committerVladimir Medic <Vladimir.Medic@imgtec.com>2015-01-29 11:33:41 +0000
commitdf464ae2248fba821eebda750f3f412f443c36b7 (patch)
tree7ce5a43d14e47165f8b159ce3d036071f1839f49 /llvm/test/MC/Disassembler/Mips/mips32r6
parented76a05c4de2a7f454d570240e71a3f17bbc3f30 (diff)
downloadbcm5719-llvm-df464ae2248fba821eebda750f3f412f443c36b7.tar.gz
bcm5719-llvm-df464ae2248fba821eebda750f3f412f443c36b7.zip
[Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions.
llvm-svn: 227430
Diffstat (limited to 'llvm/test/MC/Disassembler/Mips/mips32r6')
-rw-r--r--llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt2
-rw-r--r--llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt3
-rw-r--r--llvm/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt2
3 files changed, 4 insertions, 3 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
index 85d1a0eff4e..c10d16699b7 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
@@ -144,3 +144,5 @@
0x30 0x81 0x79 0x49 # CHECK: swc2 $25, 304($16)
0x00 0x01 0x05 0xf8 # CHECK: jialc $5, 256
0x00 0x01 0x05 0xd8 # CHECK: jic $5, 256
+0x25 0x04 0xa1 0x7c # CHECK: cache 1, 8($5)
+0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
index 3c4d1e22e8c..0b78003420b 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
@@ -144,4 +144,5 @@
0x49 0x79 0x81 0x30 # CHECK: swc2 $25, 304($16)
0xf8 0x05 0x01 0x00 # CHECK: jialc $5, 256
0xd8 0x05 0x01 0x00 # CHECK: jic $5, 256
-
+0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
+0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
index dc29c0c1768..e9afd03ddd6 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-xfail-mips32r6.txt
@@ -13,5 +13,3 @@
0x60 0xc0 0x00 0x40 # CHECK: bnec $6, $zero, 256
0x60 0xa0 0x00 0x40 # CHECK: bnec $5, $zero, 256
0x60 0xa6 0x00 0x40 # CHECK: bnec $5, $6, 256
-0x7c 0xa1 0x04 0x25 # CHECK: cache 1, 8($5)
-0x7c 0xa1 0x04 0x35 # CHECK: pref 1, 8($5)
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