bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Expand)	Author	Age	Files	Lines
*	AArch64/ARM64: move ARM64 into AArch64's place	Tim Northover	2014-05-24	15	-4152/+0
*	TableGen: fix operand counting for aliases	Tim Northover	2014-05-16	1	-4/+4
*	ARM64: print correct aliases for NEON mov & mvn instructions	Tim Northover	2014-05-15	1	-5/+5
*	TableGen/ARM64: print aliases even if they have syntax variants.	Tim Northover	2014-05-15	1	-2/+2
*	AArch64/ARM64: print BFM instructions as BFI or BFXIL	Tim Northover	2014-05-01	1	-2/+2
*	ARM64: print fp immediates without using scientific notation.	Tim Northover	2014-04-30	2	-7/+7
*	ARM64: print lsr instead of lsrv for variable shifts (etc)	Tim Northover	2014-04-30	1	-8/+8
*	ARM64: use hex immediates for movz/movk instructions	Tim Northover	2014-04-30	1	-12/+12
*	ARM64: hexify printing various immediate operands	Tim Northover	2014-04-30	2	-64/+63
*	ARM64: print canonical syntax for add/sub (imm) instructions.	Tim Northover	2014-04-30	1	-8/+8
*	[ARM64] Print preferred aliases for SFBM/UBFM in InstPrinter	Bradley Smith	2014-04-25	1	-4/+4
*	[ARM64] Support crc predicate on ARM64.	Kevin Qin	2014-04-25	1	-1/+1
*	[ARM64] Enable feature predicates for NEON / FP / CRYPTO.	Kevin Qin	2014-04-23	5	-6/+6
*	[ARM64] Change SYS without a register to an alias to make disassembling more ...	Bradley Smith	2014-04-09	1	-0/+2
*	[ARM64] Correctly disassemble ISB operand as ISB not DBarrier.	Bradley Smith	2014-04-09	1	-0/+2
*	[ARM64] Properly support both apple and standard syntax for FMOV	Bradley Smith	2014-04-09	2	-1/+8
*	[ARM64] Flag setting logical/add/sub immediate instructions don't use SP.	Bradley Smith	2014-04-09	2	-0/+10
*	[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.	Bradley Smith	2014-04-09	1	-3/+7
*	[ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.	Bradley Smith	2014-04-09	1	-0/+4
*	[ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a ...	Bradley Smith	2014-04-09	1	-0/+4
*	[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.	Bradley Smith	2014-04-09	1	-0/+2
*	[ARM64] Rename LR to the UAL-compliant 'X30'.	Bradley Smith	2014-04-09	1	-4/+4
*	[ARM64] Rename FP to the UAL-compliant 'X29'.	Bradley Smith	2014-04-09	1	-4/+4
*	[ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be ...	Bradley Smith	2014-04-09	1	-0/+4
*	[ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.	Bradley Smith	2014-04-09	1	-0/+5
*	[ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have t...	Bradley Smith	2014-04-09	1	-0/+3
*	[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.	Bradley Smith	2014-04-09	1	-0/+2
*	[ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.	Bradley Smith	2014-04-09	1	-0/+4
*	[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and ...	Bradley Smith	2014-04-09	1	-0/+5
*	[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembl...	Bradley Smith	2014-04-09	1	-1/+1
*	[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to u...	Bradley Smith	2014-04-09	1	-6/+6
*	[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also...	Bradley Smith	2014-04-09	2	-24/+29
*	[ARM64] STRHro and STRBro were not being decoded at all.	Bradley Smith	2014-04-09	1	-0/+2
*	[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB i...	Bradley Smith	2014-04-09	1	-1/+10
*	[ARM64] Register-offset loads and stores with the 'option' field equal to 00x...	Bradley Smith	2014-04-09	1	-0/+7
*	ARM64: initial backend import	Tim Northover	2014-03-29	12	-0/+4072