diff options
| author | Tim Northover <tnorthover@apple.com> | 2014-05-24 12:50:23 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-05-24 12:50:23 +0000 |
| commit | 3b0846e8f76899815159389be96d7184ad015a8a (patch) | |
| tree | 3ff48b9a41b3bf5d19039bc8e0a2907b13fc4047 /llvm/test/MC/Disassembler/ARM64 | |
| parent | cc08e1fe1b3feef12a1eba31f8afcc3bbefc733e (diff) | |
| download | bcm5719-llvm-3b0846e8f76899815159389be96d7184ad015a8a.tar.gz bcm5719-llvm-3b0846e8f76899815159389be96d7184ad015a8a.zip | |
AArch64/ARM64: move ARM64 into AArch64's place
This commit starts with a "git mv ARM64 AArch64" and continues out
from there, renaming the C++ classes, intrinsics, and other
target-local objects for consistency.
"ARM64" test directories are also moved, and tests that began their
life in ARM64 use an arm64 triple, those from AArch64 use an aarch64
triple. Both should be equivalent though.
This finishes the AArch64 merge, and everyone should feel free to
continue committing as normal now.
llvm-svn: 209577
Diffstat (limited to 'llvm/test/MC/Disassembler/ARM64')
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/advsimd.txt | 2283 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/arithmetic.txt | 526 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/basic-a64-undefined.txt | 31 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/bitfield.txt | 29 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/branch.txt | 75 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/canonical-form.txt | 21 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/crc32.txt | 18 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/crypto.txt | 47 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/invalid-logical.txt | 6 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/lit.local.cfg | 5 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/logical.txt | 223 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/memory.txt | 564 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/non-apple-fmov.txt | 7 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/scalar-fp.txt | 255 | ||||
| -rw-r--r-- | llvm/test/MC/Disassembler/ARM64/system.txt | 62 |
15 files changed, 0 insertions, 4152 deletions
diff --git a/llvm/test/MC/Disassembler/ARM64/advsimd.txt b/llvm/test/MC/Disassembler/ARM64/advsimd.txt deleted file mode 100644 index cceee672dfd..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/advsimd.txt +++ /dev/null @@ -1,2283 +0,0 @@ -# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s - -0x00 0xb8 0x20 0x0e -0x00 0xb8 0x20 0x4e -0x00 0xb8 0x60 0x0e -0x00 0xb8 0x60 0x4e -0x00 0xb8 0xa0 0x0e -0x00 0xb8 0xa0 0x4e - -# CHECK: abs.8b v0, v0 -# CHECK: abs.16b v0, v0 -# CHECK: abs.4h v0, v0 -# CHECK: abs.8h v0, v0 -# CHECK: abs.2s v0, v0 -# CHECK: abs.4s v0, v0 - -0x00 0x84 0x20 0x0e -0x00 0x84 0x20 0x4e -0x00 0x84 0x60 0x0e -0x00 0x84 0x60 0x4e -0x00 0x84 0xa0 0x0e -0x00 0x84 0xa0 0x4e -0x00 0x84 0xe0 0x4e - -# CHECK: add.8b v0, v0, v0 -# CHECK: add.16b v0, v0, v0 -# CHECK: add.4h v0, v0, v0 -# CHECK: add.8h v0, v0, v0 -# CHECK: add.2s v0, v0, v0 -# CHECK: add.4s v0, v0, v0 -# CHECK: add.2d v0, v0, v0 - -0x41 0x84 0xe3 0x5e - -# CHECK: add d1, d2, d3 - -0x00 0x40 0x20 0x0e -0x00 0x40 0x20 0x4e -0x00 0x40 0x60 0x0e -0x00 0x40 0x60 0x4e -0x00 0x40 0xa0 0x0e -0x00 0x40 0xa0 0x4e - -# CHECK: addhn.8b v0, v0, v0 -# CHECK: addhn2.16b v0, v0, v0 -# CHECK: addhn.4h v0, v0, v0 -# CHECK: addhn2.8h v0, v0, v0 -# CHECK: addhn.2s v0, v0, v0 -# CHECK: addhn2.4s v0, v0, v0 - -0x00 0xbc 0x20 0x0e -0x00 0xbc 0x20 0x4e -0x00 0xbc 0x60 0x0e -0x00 0xbc 0x60 0x4e -0x00 0xbc 0xa0 0x0e -0x00 0xbc 0xa0 0x4e -0x00 0xbc 0xe0 0x4e - -# CHECK: addp.8b v0, v0, v0 -# CHECK: addp.16b v0, v0, v0 -# CHECK: addp.4h v0, v0, v0 -# CHECK: addp.8h v0, v0, v0 -# CHECK: addp.2s v0, v0, v0 -# CHECK: addp.4s v0, v0, v0 -# CHECK: addp.2d v0, v0, v0 - -0x00 0xb8 0xf1 0x5e - -# CHECK: addp.2d d0, v0 - -0x00 0xb8 0x31 0x0e -0x00 0xb8 0x31 0x4e -0x00 0xb8 0x71 0x0e -0x00 0xb8 0x71 0x4e -0x00 0xb8 0xb1 0x4e - -# CHECK: addv.8b b0, v0 -# CHECK: addv.16b b0, v0 -# CHECK: addv.4h h0, v0 -# CHECK: addv.8h h0, v0 -# CHECK: addv.4s s0, v0 - - -# INS/DUP -0x60 0x0c 0x08 0x4e -0x60 0x0c 0x04 0x4e -0x60 0x0c 0x04 0x0e -0x60 0x0c 0x02 0x4e -0x60 0x0c 0x02 0x0e -0x60 0x0c 0x01 0x4e -0x60 0x0c 0x01 0x0e - -# CHECK: dup.2d v0, x3 -# CHECK: dup.4s v0, w3 -# CHECK: dup.2s v0, w3 -# CHECK: dup.8h v0, w3 -# CHECK: dup.4h v0, w3 -# CHECK: dup.16b v0, w3 -# CHECK: dup.8b v0, w3 - -0x60 0x04 0x18 0x4e -0x60 0x04 0x0c 0x0e -0x60 0x04 0x0c 0x4e -0x60 0x04 0x06 0x0e -0x60 0x04 0x06 0x4e -0x60 0x04 0x03 0x0e -0x60 0x04 0x03 0x4e - -# CHECK: dup.2d v0, v3[1] -# CHECK: dup.2s v0, v3[1] -# CHECK: dup.4s v0, v3[1] -# CHECK: dup.4h v0, v3[1] -# CHECK: dup.8h v0, v3[1] -# CHECK: dup.8b v0, v3[1] -# CHECK: dup.16b v0, v3[1] - - -0x43 0x2c 0x14 0x4e -0x43 0x2c 0x14 0x4e -0x43 0x3c 0x14 0x0e -0x43 0x3c 0x14 0x0e -0x43 0x3c 0x18 0x4e -0x43 0x3c 0x18 0x4e - -# CHECK: smov.s x3, v2[2] -# CHECK: smov.s x3, v2[2] -# CHECK: mov.s w3, v2[2] -# CHECK: mov.s w3, v2[2] -# CHECK: mov.d x3, v2[1] -# CHECK: mov.d x3, v2[1] - -0xa2 0x1c 0x18 0x4e -0xa2 0x1c 0x0c 0x4e -0xa2 0x1c 0x06 0x4e -0xa2 0x1c 0x03 0x4e - -0xa2 0x1c 0x18 0x4e -0xa2 0x1c 0x0c 0x4e -0xa2 0x1c 0x06 0x4e -0xa2 0x1c 0x03 0x4e - -# CHECK: ins.d v2[1], x5 -# CHECK: ins.s v2[1], w5 -# CHECK: ins.h v2[1], w5 -# CHECK: ins.b v2[1], w5 - -# CHECK: ins.d v2[1], x5 -# CHECK: ins.s v2[1], w5 -# CHECK: ins.h v2[1], w5 -# CHECK: ins.b v2[1], w5 - -0xe2 0x45 0x18 0x6e -0xe2 0x25 0x0c 0x6e -0xe2 0x15 0x06 0x6e -0xe2 0x0d 0x03 0x6e - -0xe2 0x05 0x18 0x6e -0xe2 0x45 0x1c 0x6e -0xe2 0x35 0x1e 0x6e -0xe2 0x2d 0x15 0x6e - -# CHECK: ins.d v2[1], v15[1] -# CHECK: ins.s v2[1], v15[1] -# CHECK: ins.h v2[1], v15[1] -# CHECK: ins.b v2[1], v15[1] - -# CHECK: ins.d v2[1], v15[0] -# CHECK: ins.s v2[3], v15[2] -# CHECK: ins.h v2[7], v15[3] -# CHECK: ins.b v2[10], v15[5] - -0x00 0x1c 0x20 0x0e -0x00 0x1c 0x20 0x4e - -# CHECK: and.8b v0, v0, v0 -# CHECK: and.16b v0, v0, v0 - -0x00 0x1c 0x60 0x0e - -# CHECK: bic.8b v0, v0, v0 - -0x00 0x8c 0x20 0x2e -0x00 0x3c 0x20 0x0e -0x00 0x34 0x20 0x0e -0x00 0x34 0x20 0x2e -0x00 0x3c 0x20 0x2e -0x00 0x8c 0x20 0x0e -0x00 0xd4 0xa0 0x2e -0x00 0xec 0x20 0x2e -0x00 0xec 0xa0 0x2e -0x00 0xd4 0x20 0x2e -0x00 0xd4 0x20 0x0e -0x00 0xe4 0x20 0x0e -0x00 0xe4 0x20 0x2e -0x00 0xe4 0xa0 0x2e -0x00 0xfc 0x20 0x2e -0x00 0xc4 0x20 0x2e -0x00 0xc4 0x20 0x0e -0x00 0xf4 0x20 0x2e -0x00 0xf4 0x20 0x0e -0x00 0xc4 0xa0 0x2e -0x00 0xc4 0xa0 0x0e -0x00 0xf4 0xa0 0x2e -0x00 0xf4 0xa0 0x0e -0x00 0xcc 0x20 0x0e -0x00 0xcc 0xa0 0x0e -0x00 0xdc 0x20 0x0e -0x00 0xdc 0x20 0x2e -0x00 0xfc 0x20 0x0e -0x00 0xfc 0xa0 0x0e -0x00 0xd4 0xa0 0x0e -0x00 0x94 0x20 0x0e -0x00 0x94 0x20 0x2e -0x00 0x9c 0x20 0x0e -0x00 0x9c 0x20 0x2e -0x00 0x7c 0x20 0x0e -0x00 0x74 0x20 0x0e -0x00 0x04 0x20 0x0e -0x00 0x24 0x20 0x0e -0x00 0xa4 0x20 0x0e -0x00 0x64 0x20 0x0e -0x00 0xac 0x20 0x0e -0x00 0x6c 0x20 0x0e -0x00 0x0c 0x20 0x0e -0x00 0xb4 0x60 0x0e -0x00 0xb4 0x60 0x2e -0x00 0x5c 0x20 0x0e -0x00 0x4c 0x20 0x0e -0x00 0x2c 0x20 0x0e -0x00 0x14 0x20 0x0e -0x00 0x54 0x20 0x0e -0x00 0x44 0x20 0x0e -0x00 0x84 0x20 0x2e -0x00 0x7c 0x20 0x2e -0x00 0x74 0x20 0x2e -0x00 0x04 0x20 0x2e -0x00 0x24 0x20 0x2e -0x00 0xa4 0x20 0x2e -0x00 0x64 0x20 0x2e -0x00 0xac 0x20 0x2e -0x00 0x6c 0x20 0x2e -0x00 0x0c 0x20 0x2e -0x00 0x5c 0x20 0x2e -0x00 0x4c 0x20 0x2e -0x00 0x2c 0x20 0x2e -0x00 0x14 0x20 0x2e -0x00 0x54 0x20 0x2e -0x00 0x44 0x20 0x2e - -# CHECK: cmeq.8b v0, v0, v0 -# CHECK: cmge.8b v0, v0, v0 -# CHECK: cmgt.8b v0, v0, v0 -# CHECK: cmhi.8b v0, v0, v0 -# CHECK: cmhs.8b v0, v0, v0 -# CHECK: cmtst.8b v0, v0, v0 -# CHECK: fabd.2s v0, v0, v0 -# CHECK: facge.2s v0, v0, v0 -# CHECK: facgt.2s v0, v0, v0 -# CHECK: faddp.2s v0, v0, v0 -# CHECK: fadd.2s v0, v0, v0 -# CHECK: fcmeq.2s v0, v0, v0 -# CHECK: fcmge.2s v0, v0, v0 -# CHECK: fcmgt.2s v0, v0, v0 -# CHECK: fdiv.2s v0, v0, v0 -# CHECK: fmaxnmp.2s v0, v0, v0 -# CHECK: fmaxnm.2s v0, v0, v0 -# CHECK: fmaxp.2s v0, v0, v0 -# CHECK: fmax.2s v0, v0, v0 -# CHECK: fminnmp.2s v0, v0, v0 -# CHECK: fminnm.2s v0, v0, v0 -# CHECK: fminp.2s v0, v0, v0 -# CHECK: fmin.2s v0, v0, v0 -# CHECK: fmla.2s v0, v0, v0 -# CHECK: fmls.2s v0, v0, v0 -# CHECK: fmulx.2s v0, v0, v0 -# CHECK: fmul.2s v0, v0, v0 -# CHECK: frecps.2s v0, v0, v0 -# CHECK: frsqrts.2s v0, v0, v0 -# CHECK: fsub.2s v0, v0, v0 -# CHECK: mla.8b v0, v0, v0 -# CHECK: mls.8b v0, v0, v0 -# CHECK: mul.8b v0, v0, v0 -# CHECK: pmul.8b v0, v0, v0 -# CHECK: saba.8b v0, v0, v0 -# CHECK: sabd.8b v0, v0, v0 -# CHECK: shadd.8b v0, v0, v0 -# CHECK: shsub.8b v0, v0, v0 -# CHECK: smaxp.8b v0, v0, v0 -# CHECK: smax.8b v0, v0, v0 -# CHECK: sminp.8b v0, v0, v0 -# CHECK: smin.8b v0, v0, v0 -# CHECK: sqadd.8b v0, v0, v0 -# CHECK: sqdmulh.4h v0, v0, v0 -# CHECK: sqrdmulh.4h v0, v0, v0 -# CHECK: sqrshl.8b v0, v0, v0 -# CHECK: sqshl.8b v0, v0, v0 -# CHECK: sqsub.8b v0, v0, v0 -# CHECK: srhadd.8b v0, v0, v0 -# CHECK: srshl.8b v0, v0, v0 -# CHECK: sshl.8b v0, v0, v0 -# CHECK: sub.8b v0, v0, v0 -# CHECK: uaba.8b v0, v0, v0 -# CHECK: uabd.8b v0, v0, v0 -# CHECK: uhadd.8b v0, v0, v0 -# CHECK: uhsub.8b v0, v0, v0 -# CHECK: umaxp.8b v0, v0, v0 -# CHECK: umax.8b v0, v0, v0 -# CHECK: uminp.8b v0, v0, v0 -# CHECK: umin.8b v0, v0, v0 -# CHECK: uqadd.8b v0, v0, v0 -# CHECK: uqrshl.8b v0, v0, v0 -# CHECK: uqshl.8b v0, v0, v0 -# CHECK: uqsub.8b v0, v0, v0 -# CHECK: urhadd.8b v0, v0, v0 -# CHECK: urshl.8b v0, v0, v0 -# CHECK: ushl.8b v0, v0, v0 - -0x00 0x1c 0xe0 0x2e -0x00 0x1c 0xa0 0x2e -0x00 0x1c 0x60 0x2e -0x00 0x1c 0x20 0x2e -0x00 0x1c 0xe0 0x0e -0x00 0x1c 0xa1 0x0e - -# CHECK: bif.8b v0, v0, v0 -# CHECK: bit.8b v0, v0, v0 -# CHECK: bsl.8b v0, v0, v0 -# CHECK: eor.8b v0, v0, v0 -# CHECK: orn.8b v0, v0, v0 -# CHECK: orr.8b v0, v0, v1 - -0x00 0x68 0x20 0x0e -0x00 0x68 0x20 0x4e -0x00 0x68 0x60 0x0e -0x00 0x68 0x60 0x4e -0x00 0x68 0xa0 0x0e -0x00 0x68 0xa0 0x4e - -# CHECK: sadalp.4h v0, v0 -# CHECK: sadalp.8h v0, v0 -# CHECK: sadalp.2s v0, v0 -# CHECK: sadalp.4s v0, v0 -# CHECK: sadalp.1d v0, v0 -# CHECK: sadalp.2d v0, v0 - -0x00 0x48 0x20 0x0e -0x00 0x48 0x20 0x2e -0x00 0x58 0x20 0x0e -0x00 0xf8 0xa0 0x0e -0x00 0xc8 0x21 0x0e -0x00 0xc8 0x21 0x2e -0x00 0xb8 0x21 0x0e -0x00 0xb8 0x21 0x2e -0x00 0xa8 0x21 0x0e -0x00 0xa8 0x21 0x2e -0x00 0xa8 0xa1 0x0e -0x00 0xa8 0xa1 0x2e -0x00 0xb8 0xa1 0x0e -0x00 0xb8 0xa1 0x2e -0x00 0xf8 0xa0 0x2e -0x00 0xd8 0xa1 0x0e -0x00 0xd8 0xa1 0x2e -0x00 0xf8 0xa1 0x2e -0x00 0xb8 0x20 0x2e -0x00 0x58 0x20 0x2e -0x00 0x58 0x60 0x2e -0x00 0x18 0x20 0x0e -0x00 0x08 0x20 0x2e -0x00 0x08 0x20 0x0e -0x00 0x68 0x20 0x0e -0x00 0x28 0x20 0x0e -0x00 0xd8 0x21 0x0e -0x00 0x38 0x21 0x2e -0x00 0x78 0x20 0x0e -0x00 0x78 0x20 0x2e -0x00 0x48 0x21 0x0e -0x00 0x28 0x21 0x2e -0x00 0x38 0x20 0x0e -0x00 0x68 0x20 0x2e -0x00 0x28 0x20 0x2e -0x00 0xd8 0x21 0x2e -0x00 0x48 0x21 0x2e -0x00 0xc8 0xa1 0x0e -0x00 0xc8 0xa1 0x2e -0x00 0x38 0x20 0x2e -0x00 0x28 0x21 0x0e -0x00 0x48 0x20 0x0e -0x00 0x48 0x20 0x2e -0x00 0x58 0x20 0x0e -0x00 0xf8 0xa0 0x0e -0x00 0xc8 0x21 0x0e -0x00 0xc8 0x21 0x2e -0x00 0xb8 0x21 0x0e -0x00 0xb8 0x21 0x2e -0x00 0xa8 0x21 0x0e -0x00 0xa8 0x21 0x2e -0x00 0xa8 0xa1 0x0e -0x00 0xa8 0xa1 0x2e -0x00 0xb8 0xa1 0x0e -0x00 0xb8 0xa1 0x2e -0x00 0xf8 0xa0 0x2e -0x00 0xd8 0xa1 0x0e -0x00 0xd8 0xa1 0x2e -0x00 0xf8 0xa1 0x2e -0x00 0xb8 0x20 0x2e -0x00 0x58 0x20 0x2e -0x00 0x58 0x60 0x2e -0x00 0x18 0x20 0x0e -0x00 0x08 0x20 0x2e -0x00 0x08 0x20 0x0e -0x00 0x68 0x20 0x0e -0x00 0x28 0x20 0x0e -0x00 0xd8 0x21 0x0e -0x00 0x38 0x21 0x2e -0x00 0x78 0x20 0x0e -0x00 0x78 0x20 0x2e -0x00 0x48 0x21 0x0e -0x00 0x28 0x21 0x2e -0x00 0x38 0x20 0x0e -0x00 0x68 0x20 0x2e -0x00 0x28 0x20 0x2e -0x00 0xd8 0x21 0x2e -0x00 0x48 0x21 0x2e -0x00 0xc8 0xa1 0x0e -0x00 0xc8 0xa1 0x2e -0x00 0x38 0x20 0x2e -0x00 0x28 0x21 0x0e - -# CHECK: cls.8b v0, v0 -# CHECK: clz.8b v0, v0 -# CHECK: cnt.8b v0, v0 -# CHECK: fabs.2s v0, v0 -# CHECK: fcvtas.2s v0, v0 -# CHECK: fcvtau.2s v0, v0 -# CHECK: fcvtms.2s v0, v0 -# CHECK: fcvtmu.2s v0, v0 -# CHECK: fcvtns.2s v0, v0 -# CHECK: fcvtnu.2s v0, v0 -# CHECK: fcvtps.2s v0, v0 -# CHECK: fcvtpu.2s v0, v0 -# CHECK: fcvtzs.2s v0, v0 -# CHECK: fcvtzu.2s v0, v0 -# CHECK: fneg.2s v0, v0 -# CHECK: frecpe.2s v0, v0 -# CHECK: frsqrte.2s v0, v0 -# CHECK: fsqrt.2s v0, v0 -# CHECK: neg.8b v0, v0 -# CHECK: mvn.8b v0, v0 -# CHECK: rbit.8b v0, v0 -# CHECK: rev16.8b v0, v0 -# CHECK: rev32.8b v0, v0 -# CHECK: rev64.8b v0, v0 -# CHECK: sadalp.4h v0, v0 -# CHECK: saddlp.4h v0, v0 -# CHECK: scvtf.2s v0, v0 -# CHECK: shll.8h v0, v0, #8 -# CHECK: sqabs.8b v0, v0 -# CHECK: sqneg.8b v0, v0 -# CHECK: sqxtn.8b v0, v0 -# CHECK: sqxtun.8b v0, v0 -# CHECK: suqadd.8b v0, v0 -# CHECK: uadalp.4h v0, v0 -# CHECK: uaddlp.4h v0, v0 -# CHECK: ucvtf.2s v0, v0 -# CHECK: uqxtn.8b v0, v0 -# CHECK: urecpe.2s v0, v0 -# CHECK: ursqrte.2s v0, v0 -# CHECK: usqadd.8b v0, v0 -# CHECK: xtn.8b v0, v0 - -0x00 0x98 0x20 0x0e -0x00 0x98 0x20 0x4e -0x00 0x98 0x60 0x0e -0x00 0x98 0x60 0x4e -0x00 0x98 0xa0 0x0e -0x00 0x98 0xa0 0x4e -0x00 0x98 0xe0 0x4e - -# CHECK: cmeq.8b v0, v0, #0 -# CHECK: cmeq.16b v0, v0, #0 -# CHECK: cmeq.4h v0, v0, #0 -# CHECK: cmeq.8h v0, v0, #0 -# CHECK: cmeq.2s v0, v0, #0 -# CHECK: cmeq.4s v0, v0, #0 -# CHECK: cmeq.2d v0, v0, #0 - -0x00 0x88 0x20 0x2e -0x00 0x88 0x20 0x0e -0x00 0x98 0x20 0x2e -0x00 0xa8 0x20 0x0e -0x00 0xd8 0xa0 0x0e -0x00 0xc8 0xa0 0x2e -0x00 0xc8 0xa0 0x0e -0x00 0xd8 0xa0 0x2e -0x00 0xe8 0xa0 0x0e - -# CHECK: cmge.8b v0, v0, #0 -# CHECK: cmgt.8b v0, v0, #0 -# CHECK: cmle.8b v0, v0, #0 -# CHECK: cmlt.8b v0, v0, #0 -# CHECK: fcmeq.2s v0, v0, #0 -# CHECK: fcmge.2s v0, v0, #0 -# CHECK: fcmgt.2s v0, v0, #0 -# CHECK: fcmle.2s v0, v0, #0 -# CHECK: fcmlt.2s v0, v0, #0 - -0x00 0x78 0x21 0x0e -0x00 0x78 0x21 0x4e -0x00 0x78 0x61 0x0e -0x00 0x78 0x61 0x4e -0x00 0x68 0x21 0x0e -0x00 0x68 0x21 0x4e -0x00 0x68 0x61 0x0e -0x00 0x68 0x61 0x4e -0x00 0x68 0x61 0x2e -0x00 0x68 0x61 0x6e - -# CHECK: fcvtl v0.4s, v0.4h -# CHECK: fcvtl2 v0.4s, v0.8h -# CHECK: fcvtl v0.2d, v0.2s -# CHECK: fcvtl2 v0.2d, v0.4s -# CHECK: fcvtn v0.4h, v0.4s -# CHECK: fcvtn2 v0.8h, v0.4s -# CHECK: fcvtn v0.2s, v0.2d -# CHECK: fcvtn2 v0.4s, v0.2d -# CHECK: fcvtxn v0.2s, v0.2d -# CHECK: fcvtxn2 v0.4s, v0.2d - -#===-------------------------------------------------------------------------=== -# AdvSIMD modified immediate instructions -#===-------------------------------------------------------------------------=== - -0x20 0x14 0x00 0x2f -0x20 0x34 0x00 0x2f -0x20 0x54 0x00 0x2f -0x20 0x74 0x00 0x2f - -# CHECK: bic.2s v0, #0x1 -# CHECK: bic.2s v0, #0x1, lsl #8 -# CHECK: bic.2s v0, #0x1, lsl #16 -# CHECK: bic.2s v0, #0x1, lsl #24 - -0x20 0x94 0x00 0x2f -0x20 0x94 0x00 0x2f -0x20 0xb4 0x00 0x2f - -# CHECK: bic.4h v0, #0x1 -# CHECK: bic.4h v0, #0x1 -# FIXME: bic.4h v0, #0x1, lsl #8 -# 'bic.4h' should be selected over "fcvtnu.2s v0, v1, #0" - -0x20 0x14 0x00 0x6f -0x20 0x34 0x00 0x6f -0x20 0x54 0x00 0x6f -0x20 0x74 0x00 0x6f - -# CHECK: bic.4s v0, #0x1 -# CHECK: bic.4s v0, #0x1, lsl #8 -# CHECK: bic.4s v0, #0x1, lsl #16 -# CHECK: bic.4s v0, #0x1, lsl #24 - -0x20 0x94 0x00 0x6f -0x20 0xb4 0x00 0x6f - -# CHECK: bic.8h v0, #0x1 -# FIXME: bic.8h v0, #0x1, lsl #8 -# "bic.8h" should be selected over "fcvtnu.4s v0, v1, #0" - -0x00 0xf4 0x02 0x6f - -# CHECK: fmov.2d v0, #0.12500000 - -0x00 0xf4 0x02 0x0f -0x00 0xf4 0x02 0x4f - -# CHECK: fmov.2s v0, #0.12500000 -# CHECK: fmov.4s v0, #0.12500000 - -0x20 0x14 0x00 0x0f -0x20 0x34 0x00 0x0f -0x20 0x54 0x00 0x0f -0x20 0x74 0x00 0x0f - -# CHECK: orr.2s v0, #0x1 -# CHECK: orr.2s v0, #0x1, lsl #8 -# CHECK: orr.2s v0, #0x1, lsl #16 -# CHECK: orr.2s v0, #0x1, lsl #24 - -0x20 0x94 0x00 0x0f -0x20 0xb4 0x00 0x0f - -# CHECK: orr.4h v0, #0x1 -# FIXME: orr.4h v0, #0x1, lsl #8 -# 'orr.4h' should be selected over "fcvtns.2s v0, v1, #0" - -0x20 0x14 0x00 0x4f -0x20 0x34 0x00 0x4f -0x20 0x54 0x00 0x4f -0x20 0x74 0x00 0x4f - -# CHECK: orr.4s v0, #0x1 -# CHECK: orr.4s v0, #0x1, lsl #8 -# CHECK: orr.4s v0, #0x1, lsl #16 -# CHECK: orr.4s v0, #0x1, lsl #24 - -0x20 0x94 0x00 0x4f -0x20 0xb4 0x00 0x4f - -# CHECK: orr.8h v0, #0x1 -# CHECK: orr.8h v0, #0x1, lsl #8 - -0x21 0x70 0x40 0x0c -0x42 0xa0 0x40 0x4c -0x64 0x64 0x40 0x0c -0x87 0x24 0x40 0x4c -0x0c 0xa8 0x40 0x0c -0x0a 0x68 0x40 0x4c -0x2d 0xac 0x40 0x0c -0x4f 0x7c 0x40 0x4c -0xe0 0x03 0x40 0x0d - -# CHECK: ld1.8b { v1 }, [x1] -# CHECK: ld1.16b { v2, v3 }, [x2] -# CHECK: ld1.4h { v4, v5, v6 }, [x3] -# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4] -# CHECK: ld1.2s { v12, v13 }, [x0] -# CHECK: ld1.4s { v10, v11, v12 }, [x0] -# CHECK: ld1.1d { v13, v14 }, [x1] -# CHECK: ld1.2d { v15 }, [x2] -# CHECK: ld1.b { v0 }[0], [sp] - -0x41 0x70 0xdf 0x0c -0x41 0xa0 0xdf 0x0c -0x41 0x60 0xdf 0x0c -0x41 0x20 0xdf 0x0c -0x42 0x70 0xdf 0x4c -0x42 0xa0 0xdf 0x4c -0x42 0x60 0xdf 0x4c -0x42 0x20 0xdf 0x4c -0x64 0x74 0xdf 0x0c -0x64 0xa4 0xdf 0x0c -0x64 0x64 0xdf 0x0c -0x64 0x24 0xdf 0x0c -0x87 0x74 0xdf 0x4c -0x87 0xa4 0xdf 0x4c -0x87 0x64 0xdf 0x4c -0x87 0x24 0xdf 0x4c -0x0c 0x78 0xdf 0x0c -0x0c 0xa8 0xdf 0x0c -0x0c 0x68 0xdf 0x0c -0x0c 0x28 0xdf 0x0c -0x0a 0x78 0xdf 0x4c -0x0a 0xa8 0xdf 0x4c -0x0a 0x68 0xdf 0x4c -0x0a 0x28 0xdf 0x4c -0x2d 0x7c 0xdf 0x0c -0x2d 0xac 0xdf 0x0c -0x2d 0x6c 0xdf 0x0c -0x2d 0x2c 0xdf 0x0c -0x4f 0x7c 0xdf 0x4c -0x4f 0xac 0xdf 0x4c -0x4f 0x6c 0xdf 0x4c -0x4f 0x2c 0xdf 0x4c - -# CHECK: ld1.8b { v1 }, [x2], #8 -# CHECK: ld1.8b { v1, v2 }, [x2], #16 -# CHECK: ld1.8b { v1, v2, v3 }, [x2], #24 -# CHECK: ld1.8b { v1, v2, v3, v4 }, [x2], #32 -# CHECK: ld1.16b { v2 }, [x2], #16 -# CHECK: ld1.16b { v2, v3 }, [x2], #32 -# CHECK: ld1.16b { v2, v3, v4 }, [x2], #48 -# CHECK: ld1.16b { v2, v3, v4, v5 }, [x2], #64 -# CHECK: ld1.4h { v4 }, [x3], #8 -# CHECK: ld1.4h { v4, v5 }, [x3], #16 -# CHECK: ld1.4h { v4, v5, v6 }, [x3], #24 -# CHECK: ld1.4h { v4, v5, v6, v7 }, [x3], #32 -# CHECK: ld1.8h { v7 }, [x4], #16 -# CHECK: ld1.8h { v7, v8 }, [x4], #32 -# CHECK: ld1.8h { v7, v8, v9 }, [x4], #48 -# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], #64 -# CHECK: ld1.2s { v12 }, [x0], #8 -# CHECK: ld1.2s { v12, v13 }, [x0], #16 -# CHECK: ld1.2s { v12, v13, v14 }, [x0], #24 -# CHECK: ld1.2s { v12, v13, v14, v15 }, [x0], #32 -# CHECK: ld1.4s { v10 }, [x0], #16 -# CHECK: ld1.4s { v10, v11 }, [x0], #32 -# CHECK: ld1.4s { v10, v11, v12 }, [x0], #48 -# CHECK: ld1.4s { v10, v11, v12, v13 }, [x0], #64 -# CHECK: ld1.1d { v13 }, [x1], #8 -# CHECK: ld1.1d { v13, v14 }, [x1], #16 -# CHECK: ld1.1d { v13, v14, v15 }, [x1], #24 -# CHECK: ld1.1d { v13, v14, v15, v16 }, [x1], #32 -# CHECK: ld1.2d { v15 }, [x2], #16 -# CHECK: ld1.2d { v15, v16 }, [x2], #32 -# CHECK: ld1.2d { v15, v16, v17 }, [x2], #48 -# CHECK: ld1.2d { v15, v16, v17, v18 }, [x2], #64 - -0x21 0x70 0x00 0x0c -0x42 0xa0 0x00 0x4c -0x64 0x64 0x00 0x0c -0x87 0x24 0x00 0x4c -0x0c 0xa8 0x00 0x0c -0x0a 0x68 0x00 0x4c -0x2d 0xac 0x00 0x0c -0x4f 0x7c 0x00 0x4c - -# CHECK: st1.8b { v1 }, [x1] -# CHECK: st1.16b { v2, v3 }, [x2] -# CHECK: st1.4h { v4, v5, v6 }, [x3] -# CHECK: st1.8h { v7, v8, v9, v10 }, [x4] -# CHECK: st1.2s { v12, v13 }, [x0] -# CHECK: st1.4s { v10, v11, v12 }, [x0] -# CHECK: st1.1d { v13, v14 }, [x1] -# CHECK: st1.2d { v15 }, [x2] - -0x61 0x08 0x40 0x0d -0x82 0x84 0x40 0x4d -0xa3 0x58 0x40 0x0d -0xc4 0x80 0x40 0x4d - -# CHECK: ld1.b { v1 }[2], [x3] -# CHECK: ld1.d { v2 }[1], [x4] -# CHECK: ld1.h { v3 }[3], [x5] -# CHECK: ld1.s { v4 }[2], [x6] - -0x61 0x08 0xdf 0x0d -0x82 0x84 0xdf 0x4d -0xa3 0x58 0xdf 0x0d -0xc4 0x80 0xdf 0x4d - -# CHECK: ld1.b { v1 }[2], [x3], #1 -# CHECK: ld1.d { v2 }[1], [x4], #8 -# CHECK: ld1.h { v3 }[3], [x5], #2 -# CHECK: ld1.s { v4 }[2], [x6], #4 - -0x61 0x08 0x00 0x0d -0x82 0x84 0x00 0x4d -0xa3 0x58 0x00 0x0d -0xc4 0x80 0x00 0x4d - -# CHECK: st1.b { v1 }[2], [x3] -# CHECK: st1.d { v2 }[1], [x4] -# CHECK: st1.h { v3 }[3], [x5] -# CHECK: st1.s { v4 }[2], [x6] - -0x61 0x08 0x9f 0x0d -0x82 0x84 0x9f 0x4d -0xa3 0x58 0x9f 0x0d -0xc4 0x80 0x9f 0x4d - -# CHECK: st1.b { v1 }[2], [x3], #1 -# CHECK: st1.d { v2 }[1], [x4], #8 -# CHECK: st1.h { v3 }[3], [x5], #2 -# CHECK: st1.s { v4 }[2], [x6], #4 - -0x61 0x08 0xc4 0x0d -0x82 0x84 0xc5 0x4d -0xa3 0x58 0xc6 0x0d -0xc4 0x80 0xc7 0x4d - -# CHECK: ld1.b { v1 }[2], [x3], x4 -# CHECK: ld1.d { v2 }[1], [x4], x5 -# CHECK: ld1.h { v3 }[3], [x5], x6 -# CHECK: ld1.s { v4 }[2], [x6], x7 - -0x61 0x08 0x84 0x0d -0x82 0x84 0x85 0x4d -0xa3 0x58 0x86 0x0d -0xc4 0x80 0x87 0x4d - -# CHECK: st1.b { v1 }[2], [x3], x4 -# CHECK: st1.d { v2 }[1], [x4], x5 -# CHECK: st1.h { v3 }[3], [x5], x6 -# CHECK: st1.s { v4 }[2], [x6], x7 - -0x41 0x70 0xc3 0x0c -0x42 0xa0 0xc4 0x4c -0x64 0x64 0xc5 0x0c -0x87 0x24 0xc6 0x4c -0x0c 0xa8 0xc7 0x0c -0x0a 0x68 0xc8 0x4c -0x2d 0xac 0xc9 0x0c -0x4f 0x7c 0xca 0x4c - -# CHECK: ld1.8b { v1 }, [x2], x3 -# CHECK: ld1.16b { v2, v3 }, [x2], x4 -# CHECK: ld1.4h { v4, v5, v6 }, [x3], x5 -# CHECK: ld1.8h { v7, v8, v9, v10 }, [x4], x6 -# CHECK: ld1.2s { v12, v13 }, [x0], x7 -# CHECK: ld1.4s { v10, v11, v12 }, [x0], x8 -# CHECK: ld1.1d { v13, v14 }, [x1], x9 -# CHECK: ld1.2d { v15 }, [x2], x10 - -0x41 0x70 0x83 0x0c -0x42 0xa0 0x84 0x4c -0x64 0x64 0x85 0x0c -0x87 0x24 0x86 0x4c -0x0c 0xa8 0x87 0x0c -0x0a 0x68 0x88 0x4c -0x2d 0xac 0x89 0x0c -0x4f 0x7c 0x8a 0x4c - -# CHECK: st1.8b { v1 }, [x2], x3 -# CHECK: st1.16b { v2, v3 }, [x2], x4 -# CHECK: st1.4h { v4, v5, v6 }, [x3], x5 -# CHECK: st1.8h { v7, v8, v9, v10 }, [x4], x6 -# CHECK: st1.2s { v12, v13 }, [x0], x7 -# CHECK: st1.4s { v10, v11, v12 }, [x0], x8 -# CHECK: st1.1d { v13, v14 }, [x1], x9 -# CHECK: st1.2d { v15 }, [x2], x10 - -0x41 0x70 0x9f 0x0c -0x41 0xa0 0x9f 0x0c -0x41 0x60 0x9f 0x0c -0x41 0x20 0x9f 0x0c -0x42 0x70 0x9f 0x4c -0x42 0xa0 0x9f 0x4c -0x42 0x60 0x9f 0x4c -0x42 0x20 0x9f 0x4c -0x64 0x74 0x9f 0x0c -0x64 0xa4 0x9f 0x0c -0x64 0x64 0x9f 0x0c -0x64 0x24 0x9f 0x0c -0x87 0x74 0x9f 0x4c -0x87 0xa4 0x9f 0x4c -0x87 0x64 0x9f 0x4c -0x87 0x24 0x9f 0x4c -0x0c 0x78 0x9f 0x0c -0x0c 0xa8 0x9f 0x0c -0x0c 0x68 0x9f 0x0c -0x0c 0x28 0x9f 0x0c -0x0a 0x78 0x9f 0x4c -0x0a 0xa8 0x9f 0x4c -0x0a 0x68 0x9f 0x4c -0x0a 0x28 0x9f 0x4c -0x2d 0x7c 0x9f 0x0c -0x2d 0xac 0x9f 0x0c -0x2d 0x6c 0x9f 0x0c -0x2d 0x2c 0x9f 0x0c -0x4f 0x7c 0x9f 0x4c -0x4f 0xac 0x9f 0x4c -0x4f 0x6c 0x9f 0x4c -0x4f 0x2c 0x9f 0x4c - -# CHECK: st1.8b { v1 }, [x2], #8 -# CHECK: st1.8b { v1, v2 }, [x2], #16 -# CHECK: st1.8b { v1, v2, v3 }, [x2], #24 -# CHECK: st1.8b { v1, v2, v3, v4 }, [x2], #32 -# CHECK: st1.16b { v2 }, [x2], #16 -# CHECK: st1.16b { v2, v3 }, [x2], #32 -# CHECK: st1.16b { v2, v3, v4 }, [x2], #48 -# CHECK: st1.16b { v2, v3, v4, v5 }, [x2], #64 -# CHECK: st1.4h { v4 }, [x3], #8 -# CHECK: st1.4h { v4, v5 }, [x3], #16 -# CHECK: st1.4h { v4, v5, v6 }, [x3], #24 -# CHECK: st1.4h { v4, v5, v6, v7 }, [x3], #32 -# CHECK: st1.8h { v7 }, [x4], #16 -# CHECK: st1.8h { v7, v8 }, [x4], #32 -# CHECK: st1.8h { v7, v8, v9 }, [x4], #48 -# CHECK: st1.8h { v7, v8, v9, v10 }, [x4], #64 -# CHECK: st1.2s { v12 }, [x0], #8 -# CHECK: st1.2s { v12, v13 }, [x0], #16 -# CHECK: st1.2s { v12, v13, v14 }, [x0], #24 -# CHECK: st1.2s { v12, v13, v14, v15 }, [x0], #32 -# CHECK: st1.4s { v10 }, [x0], #16 -# CHECK: st1.4s { v10, v11 }, [x0], #32 -# CHECK: st1.4s { v10, v11, v12 }, [x0], #48 -# CHECK: st1.4s { v10, v11, v12, v13 }, [x0], #64 -# CHECK: st1.1d { v13 }, [x1], #8 -# CHECK: st1.1d { v13, v14 }, [x1], #16 -# CHECK: st1.1d { v13, v14, v15 }, [x1], #24 -# CHECK: st1.1d { v13, v14, v15, v16 }, [x1], #32 -# CHECK: st1.2d { v15 }, [x2], #16 -# CHECK: st1.2d { v15, v16 }, [x2], #32 -# CHECK: st1.2d { v15, v16, v17 }, [x2], #48 -# CHECK: st1.2d { v15, v16, v17, v18 }, [x2], #64 - -0x21 0xc0 0x40 0x0d -0x21 0xc0 0xc2 0x0d -0x64 0xc4 0x40 0x0d -0x64 0xc4 0xc5 0x0d -0xa9 0xc8 0x40 0x0d -0xa9 0xc8 0xc6 0x0d -0xec 0xcc 0x40 0x0d -0xec 0xcc 0xc8 0x0d - -# CHECK: ld1r.8b { v1 }, [x1] -# CHECK: ld1r.8b { v1 }, [x1], x2 -# CHECK: ld1r.4h { v4 }, [x3] -# CHECK: ld1r.4h { v4 }, [x3], x5 -# CHECK: ld1r.2s { v9 }, [x5] -# CHECK: ld1r.2s { v9 }, [x5], x6 -# CHECK: ld1r.1d { v12 }, [x7] -# CHECK: ld1r.1d { v12 }, [x7], x8 - -0x21 0xc0 0xdf 0x0d -0x21 0xc4 0xdf 0x0d -0x21 0xc8 0xdf 0x0d -0x21 0xcc 0xdf 0x0d - -# CHECK: ld1r.8b { v1 }, [x1], #1 -# CHECK: ld1r.4h { v1 }, [x1], #2 -# CHECK: ld1r.2s { v1 }, [x1], #4 -# CHECK: ld1r.1d { v1 }, [x1], #8 - -0x45 0x80 0x40 0x4c -0x0a 0x88 0x40 0x0c - -# CHECK: ld2.16b { v5, v6 }, [x2] -# CHECK: ld2.2s { v10, v11 }, [x0] - -0x45 0x80 0x00 0x4c -0x0a 0x88 0x00 0x0c - -# CHECK: st2.16b { v5, v6 }, [x2] -# CHECK: st2.2s { v10, v11 }, [x0] - -0x61 0x08 0x20 0x0d -0x82 0x84 0x20 0x4d -0xc3 0x50 0x20 0x0d -0xe4 0x90 0x20 0x4d - -# CHECK: st2.b { v1, v2 }[2], [x3] -# CHECK: st2.d { v2, v3 }[1], [x4] -# CHECK: st2.h { v3, v4 }[2], [x6] -# CHECK: st2.s { v4, v5 }[3], [x7] - -0x61 0x08 0xbf 0x0d -0x82 0x84 0xbf 0x4d -0xa3 0x58 0xbf 0x0d -0xc4 0x80 0xbf 0x4d - -# CHECK: st2.b { v1, v2 }[2], [x3], #2 -# CHECK: st2.d { v2, v3 }[1], [x4], #16 -# CHECK: st2.h { v3, v4 }[3], [x5], #4 -# CHECK: st2.s { v4, v5 }[2], [x6], #8 - -0x61 0x08 0x60 0x0d -0x82 0x84 0x60 0x4d -0xc3 0x50 0x60 0x0d -0xe4 0x90 0x60 0x4d - -# CHECK: ld2.b { v1, v2 }[2], [x3] -# CHECK: ld2.d { v2, v3 }[1], [x4] -# CHECK: ld2.h { v3, v4 }[2], [x6] -# CHECK: ld2.s { v4, v5 }[3], [x7] - -0x61 0x08 0xff 0x0d -0x82 0x84 0xff 0x4d -0xa3 0x58 0xff 0x0d -0xc4 0x80 0xff 0x4d - -# CHECK: ld2.b { v1, v2 }[2], [x3], #2 -# CHECK: ld2.d { v2, v3 }[1], [x4], #16 -# CHECK: ld2.h { v3, v4 }[3], [x5], #4 -# CHECK: ld2.s { v4, v5 }[2], [x6], #8 - -0x61 0x08 0xe4 0x0d -0x82 0x84 0xe6 0x4d -0xa3 0x58 0xe8 0x0d -0xc4 0x80 0xea 0x4d - -# CHECK: ld2.b { v1, v2 }[2], [x3], x4 -# CHECK: ld2.d { v2, v3 }[1], [x4], x6 -# CHECK: ld2.h { v3, v4 }[3], [x5], x8 -# CHECK: ld2.s { v4, v5 }[2], [x6], x10 - -0x61 0x08 0xa4 0x0d -0x82 0x84 0xa6 0x4d -0xa3 0x58 0xa8 0x0d -0xc4 0x80 0xaa 0x4d - -# CHECK: st2.b { v1, v2 }[2], [x3], x4 -# CHECK: st2.d { v2, v3 }[1], [x4], x6 -# CHECK: st2.h { v3, v4 }[3], [x5], x8 -# CHECK: st2.s { v4, v5 }[2], [x6], x10 - -0x64 0x84 0xc5 0x0c -0x0c 0x88 0xc7 0x0c - -# CHECK: ld2.4h { v4, v5 }, [x3], x5 -# CHECK: ld2.2s { v12, v13 }, [x0], x7 - -0x00 0x80 0xdf 0x0c -0x00 0x80 0xdf 0x4c -0x00 0x84 0xdf 0x0c -0x00 0x84 0xdf 0x4c -0x00 0x88 0xdf 0x0c -0x00 0x88 0xdf 0x4c -0x00 0x8c 0xdf 0x4c - -# CHECK: ld2.8b { v0, v1 }, [x0], #16 -# CHECK: ld2.16b { v0, v1 }, [x0], #32 -# CHECK: ld2.4h { v0, v1 }, [x0], #16 -# CHECK: ld2.8h { v0, v1 }, [x0], #32 -# CHECK: ld2.2s { v0, v1 }, [x0], #16 -# CHECK: ld2.4s { v0, v1 }, [x0], #32 -# CHECK: ld2.2d { v0, v1 }, [x0], #32 - -0x64 0x84 0x85 0x0c -0x0c 0x88 0x87 0x0c - -# CHECK: st2.4h { v4, v5 }, [x3], x5 -# CHECK: st2.2s { v12, v13 }, [x0], x7 - -0x00 0x80 0x9f 0x0c -0x00 0x80 0x9f 0x4c -0x00 0x84 0x9f 0x0c -0x00 0x84 0x9f 0x4c -0x00 0x88 0x9f 0x0c -0x00 0x88 0x9f 0x4c -0x00 0x8c 0x9f 0x4c - -# CHECK: st2.8b { v0, v1 }, [x0], #16 -# CHECK: st2.16b { v0, v1 }, [x0], #32 -# CHECK: st2.4h { v0, v1 }, [x0], #16 -# CHECK: st2.8h { v0, v1 }, [x0], #32 -# CHECK: st2.2s { v0, v1 }, [x0], #16 -# CHECK: st2.4s { v0, v1 }, [x0], #32 -# CHECK: st2.2d { v0, v1 }, [x0], #32 - -0x21 0xc0 0x60 0x0d -0x21 0xc0 0xe2 0x0d -0x21 0xc0 0x60 0x4d -0x21 0xc0 0xe2 0x4d -0x21 0xc4 0x60 0x0d -0x21 0xc4 0xe2 0x0d -0x21 0xc4 0x60 0x4d -0x21 0xc4 0xe2 0x4d -0x21 0xc8 0x60 0x0d -0x21 0xc8 0xe2 0x0d -0x21 0xcc 0x60 0x4d -0x21 0xcc 0xe2 0x4d -0x21 0xcc 0x60 0x0d -0x21 0xcc 0xe2 0x0d - -# CHECK: ld2r.8b { v1, v2 }, [x1] -# CHECK: ld2r.8b { v1, v2 }, [x1], x2 -# CHECK: ld2r.16b { v1, v2 }, [x1] -# CHECK: ld2r.16b { v1, v2 }, [x1], x2 -# CHECK: ld2r.4h { v1, v2 }, [x1] -# CHECK: ld2r.4h { v1, v2 }, [x1], x2 -# CHECK: ld2r.8h { v1, v2 }, [x1] -# CHECK: ld2r.8h { v1, v2 }, [x1], x2 -# CHECK: ld2r.2s { v1, v2 }, [x1] -# CHECK: ld2r.2s { v1, v2 }, [x1], x2 -# CHECK: ld2r.2d { v1, v2 }, [x1] -# CHECK: ld2r.2d { v1, v2 }, [x1], x2 -# CHECK: ld2r.1d { v1, v2 }, [x1] -# CHECK: ld2r.1d { v1, v2 }, [x1], x2 - -0x21 0xc0 0xff 0x0d -0x21 0xc0 0xff 0x4d -0x21 0xc4 0xff 0x0d -0x21 0xc4 0xff 0x4d -0x21 0xc8 0xff 0x0d -0x21 0xcc 0xff 0x4d -0x21 0xcc 0xff 0x0d - -# CHECK: ld2r.8b { v1, v2 }, [x1], #2 -# CHECK: ld2r.16b { v1, v2 }, [x1], #2 -# CHECK: ld2r.4h { v1, v2 }, [x1], #4 -# CHECK: ld2r.8h { v1, v2 }, [x1], #4 -# CHECK: ld2r.2s { v1, v2 }, [x1], #8 -# CHECK: ld2r.2d { v1, v2 }, [x1], #16 -# CHECK: ld2r.1d { v1, v2 }, [x1], #16 - -0x21 0x40 0x40 0x0c -0x45 0x40 0x40 0x4c -0x0a 0x48 0x40 0x0c - -# CHECK: ld3.8b { v1, v2, v3 }, [x1] -# CHECK: ld3.16b { v5, v6, v7 }, [x2] -# CHECK: ld3.2s { v10, v11, v12 }, [x0] - -0x21 0x40 0x00 0x0c -0x45 0x40 0x00 0x4c -0x0a 0x48 0x00 0x0c - -# CHECK: st3.8b { v1, v2, v3 }, [x1] -# CHECK: st3.16b { v5, v6, v7 }, [x2] -# CHECK: st3.2s { v10, v11, v12 }, [x0] - -0x61 0x28 0xc4 0x0d -0x82 0xa4 0xc5 0x4d -0xa3 0x78 0xc6 0x0d -0xc4 0xa0 0xc7 0x4d - -# CHECK: ld3.b { v1, v2, v3 }[2], [x3], x4 -# CHECK: ld3.d { v2, v3, v4 }[1], [x4], x5 -# CHECK: ld3.h { v3, v4, v5 }[3], [x5], x6 -# CHECK: ld3.s { v4, v5, v6 }[2], [x6], x7 - -0x61 0x28 0x84 0x0d -0x82 0xa4 0x85 0x4d -0xa3 0x78 0x86 0x0d -0xc4 0xa0 0x87 0x4d - -# CHECK: st3.b { v1, v2, v3 }[2], [x3], x4 -# CHECK: st3.d { v2, v3, v4 }[1], [x4], x5 -# CHECK: st3.h { v3, v4, v5 }[3], [x5], x6 -# CHECK: st3.s { v4, v5, v6 }[2], [x6], x7 - -0x61 0x28 0x9f 0x0d -0x82 0xa4 0x9f 0x4d -0xa3 0x78 0x9f 0x0d -0xc4 0xa0 0x9f 0x4d - -# CHECK: st3.b { v1, v2, v3 }[2], [x3], #3 -# CHECK: st3.d { v2, v3, v4 }[1], [x4], #24 -# CHECK: st3.h { v3, v4, v5 }[3], [x5], #6 -# CHECK: st3.s { v4, v5, v6 }[2], [x6], #12 - -0x41 0x40 0xc3 0x0c -0x42 0x40 0xc4 0x4c -0x64 0x44 0xc5 0x0c -0x87 0x44 0xc6 0x4c -0x0c 0x48 0xc7 0x0c -0x0a 0x48 0xc8 0x4c -0x4f 0x4c 0xca 0x4c - -# CHECK: ld3.8b { v1, v2, v3 }, [x2], x3 -# CHECK: ld3.16b { v2, v3, v4 }, [x2], x4 -# CHECK: ld3.4h { v4, v5, v6 }, [x3], x5 -# CHECK: ld3.8h { v7, v8, v9 }, [x4], x6 -# CHECK: ld3.2s { v12, v13, v14 }, [x0], x7 -# CHECK: ld3.4s { v10, v11, v12 }, [x0], x8 -# CHECK: ld3.2d { v15, v16, v17 }, [x2], x10 - -0x00 0x40 0xdf 0x0c -0x00 0x40 0xdf 0x4c -0x00 0x44 0xdf 0x0c -0x00 0x44 0xdf 0x4c -0x00 0x48 0xdf 0x0c -0x00 0x48 0xdf 0x4c -0x00 0x4c 0xdf 0x4c - -# CHECK: ld3.8b { v0, v1, v2 }, [x0], #24 -# CHECK: ld3.16b { v0, v1, v2 }, [x0], #48 -# CHECK: ld3.4h { v0, v1, v2 }, [x0], #24 -# CHECK: ld3.8h { v0, v1, v2 }, [x0], #48 -# CHECK: ld3.2s { v0, v1, v2 }, [x0], #24 -# CHECK: ld3.4s { v0, v1, v2 }, [x0], #48 -# CHECK: ld3.2d { v0, v1, v2 }, [x0], #48 - -0x41 0x40 0x83 0x0c -0x42 0x40 0x84 0x4c -0x64 0x44 0x85 0x0c -0x87 0x44 0x86 0x4c -0x0c 0x48 0x87 0x0c -0x0a 0x48 0x88 0x4c -0x4f 0x4c 0x8a 0x4c - -# CHECK: st3.8b { v1, v2, v3 }, [x2], x3 -# CHECK: st3.16b { v2, v3, v4 }, [x2], x4 -# CHECK: st3.4h { v4, v5, v6 }, [x3], x5 -# CHECK: st3.8h { v7, v8, v9 }, [x4], x6 -# CHECK: st3.2s { v12, v13, v14 }, [x0], x7 -# CHECK: st3.4s { v10, v11, v12 }, [x0], x8 -# CHECK: st3.2d { v15, v16, v17 }, [x2], x10 - -0x00 0x40 0x9f 0x0c -0x00 0x40 0x9f 0x4c -0x00 0x44 0x9f 0x0c -0x00 0x44 0x9f 0x4c -0x00 0x48 0x9f 0x0c -0x00 0x48 0x9f 0x4c -0x00 0x4c 0x9f 0x4c - -# CHECK: st3.8b { v0, v1, v2 }, [x0], #24 -# CHECK: st3.16b { v0, v1, v2 }, [x0], #48 -# CHECK: st3.4h { v0, v1, v2 }, [x0], #24 -# CHECK: st3.8h { v0, v1, v2 }, [x0], #48 -# CHECK: st3.2s { v0, v1, v2 }, [x0], #24 -# CHECK: st3.4s { v0, v1, v2 }, [x0], #48 -# CHECK: st3.2d { v0, v1, v2 }, [x0], #48 - -0x61 0x28 0x40 0x0d -0x82 0xa4 0x40 0x4d -0xc3 0x70 0x40 0x0d -0xe4 0xb0 0x40 0x4d - -# CHECK: ld3.b { v1, v2, v3 }[2], [x3] -# CHECK: ld3.d { v2, v3, v4 }[1], [x4] -# CHECK: ld3.h { v3, v4, v5 }[2], [x6] -# CHECK: ld3.s { v4, v5, v6 }[3], [x7] - -0x61 0x28 0xdf 0x0d -0x82 0xa4 0xdf 0x4d -0xa3 0x78 0xdf 0x0d -0xc4 0xa0 0xdf 0x4d - -# CHECK: ld3.b { v1, v2, v3 }[2], [x3], #3 -# CHECK: ld3.d { v2, v3, v4 }[1], [x4], #24 -# CHECK: ld3.h { v3, v4, v5 }[3], [x5], #6 -# CHECK: ld3.s { v4, v5, v6 }[2], [x6], #12 - -0x61 0x28 0x00 0x0d -0x82 0xa4 0x00 0x4d -0xc3 0x70 0x00 0x0d -0xe4 0xb0 0x00 0x4d - -# CHECK: st3.b { v1, v2, v3 }[2], [x3] -# CHECK: st3.d { v2, v3, v4 }[1], [x4] -# CHECK: st3.h { v3, v4, v5 }[2], [x6] -# CHECK: st3.s { v4, v5, v6 }[3], [x7] - -0x21 0xe0 0x40 0x0d -0x21 0xe0 0xc2 0x0d -0x21 0xe0 0x40 0x4d -0x21 0xe0 0xc2 0x4d -0x21 0xe4 0x40 0x0d -0x21 0xe4 0xc2 0x0d -0x21 0xe4 0x40 0x4d -0x21 0xe4 0xc2 0x4d -0x21 0xe8 0x40 0x0d -0x21 0xe8 0xc2 0x0d -0x21 0xec 0x40 0x4d -0x21 0xec 0xc2 0x4d -0x21 0xec 0x40 0x0d -0x21 0xec 0xc2 0x0d - -# CHECK: ld3r.8b { v1, v2, v3 }, [x1] -# CHECK: ld3r.8b { v1, v2, v3 }, [x1], x2 -# CHECK: ld3r.16b { v1, v2, v3 }, [x1] -# CHECK: ld3r.16b { v1, v2, v3 }, [x1], x2 -# CHECK: ld3r.4h { v1, v2, v3 }, [x1] -# CHECK: ld3r.4h { v1, v2, v3 }, [x1], x2 -# CHECK: ld3r.8h { v1, v2, v3 }, [x1] -# CHECK: ld3r.8h { v1, v2, v3 }, [x1], x2 -# CHECK: ld3r.2s { v1, v2, v3 }, [x1] -# CHECK: ld3r.2s { v1, v2, v3 }, [x1], x2 -# CHECK: ld3r.2d { v1, v2, v3 }, [x1] -# CHECK: ld3r.2d { v1, v2, v3 }, [x1], x2 -# CHECK: ld3r.1d { v1, v2, v3 }, [x1] -# CHECK: ld3r.1d { v1, v2, v3 }, [x1], x2 - -0x21 0xe0 0xdf 0x0d -0x21 0xe0 0xdf 0x4d -0x21 0xe4 0xdf 0x0d -0x21 0xe4 0xdf 0x4d -0x21 0xe8 0xdf 0x0d -0x21 0xec 0xdf 0x4d -0x21 0xec 0xdf 0x0d - -# CHECK: ld3r.8b { v1, v2, v3 }, [x1], #3 -# CHECK: ld3r.16b { v1, v2, v3 }, [x1], #3 -# CHECK: ld3r.4h { v1, v2, v3 }, [x1], #6 -# CHECK: ld3r.8h { v1, v2, v3 }, [x1], #6 -# CHECK: ld3r.2s { v1, v2, v3 }, [x1], #12 -# CHECK: ld3r.2d { v1, v2, v3 }, [x1], #24 -# CHECK: ld3r.1d { v1, v2, v3 }, [x1], #24 - -0x21 0x00 0x40 0x0c -0x45 0x00 0x40 0x4c -0x0a 0x08 0x40 0x0c - -# CHECK: ld4.8b { v1, v2, v3, v4 }, [x1] -# CHECK: ld4.16b { v5, v6, v7, v8 }, [x2] -# CHECK: ld4.2s { v10, v11, v12, v13 }, [x0] - -0x21 0x00 0x00 0x0c -0x45 0x00 0x00 0x4c -0x0a 0x08 0x00 0x0c - -# CHECK: st4.8b { v1, v2, v3, v4 }, [x1] -# CHECK: st4.16b { v5, v6, v7, v8 }, [x2] -# CHECK: st4.2s { v10, v11, v12, v13 }, [x0] - -0x61 0x28 0xe4 0x0d -0x82 0xa4 0xe5 0x4d -0xa3 0x78 0xe6 0x0d -0xc4 0xa0 0xe7 0x4d - -# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], x4 -# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], x5 -# CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], x6 -# CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], x7 - -0x61 0x28 0xff 0x0d -0x82 0xa4 0xff 0x4d -0xa3 0x78 0xff 0x0d -0xc4 0xa0 0xff 0x4d - -# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3], #4 -# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4], #32 -# CHECK: ld4.h { v3, v4, v5, v6 }[3], [x5], #8 -# CHECK: ld4.s { v4, v5, v6, v7 }[2], [x6], #16 - -0x61 0x28 0xa4 0x0d -0x82 0xa4 0xa5 0x4d -0xa3 0x78 0xa6 0x0d -0xc4 0xa0 0xa7 0x4d - -# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], x4 -# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], x5 -# CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], x6 -# CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], x7 - -0x61 0x28 0xbf 0x0d -0x82 0xa4 0xbf 0x4d -0xa3 0x78 0xbf 0x0d -0xc4 0xa0 0xbf 0x4d - -# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3], #4 -# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4], #32 -# CHECK: st4.h { v3, v4, v5, v6 }[3], [x5], #8 -# CHECK: st4.s { v4, v5, v6, v7 }[2], [x6], #16 - -0x41 0x00 0xc3 0x0c -0x42 0x00 0xc4 0x4c -0x64 0x04 0xc5 0x0c -0x87 0x04 0xc6 0x4c -0x0c 0x08 0xc7 0x0c -0x0a 0x08 0xc8 0x4c -0x4f 0x0c 0xca 0x4c - -# CHECK: ld4.8b { v1, v2, v3, v4 }, [x2], x3 -# CHECK: ld4.16b { v2, v3, v4, v5 }, [x2], x4 -# CHECK: ld4.4h { v4, v5, v6, v7 }, [x3], x5 -# CHECK: ld4.8h { v7, v8, v9, v10 }, [x4], x6 -# CHECK: ld4.2s { v12, v13, v14, v15 }, [x0], x7 -# CHECK: ld4.4s { v10, v11, v12, v13 }, [x0], x8 -# CHECK: ld4.2d { v15, v16, v17, v18 }, [x2], x10 - -0x00 0x00 0xdf 0x0c -0x00 0x00 0xdf 0x4c -0x00 0x04 0xdf 0x0c -0x00 0x04 0xdf 0x4c -0x00 0x08 0xdf 0x0c -0x00 0x08 0xdf 0x4c -0x00 0x0c 0xdf 0x4c - -# CHECK: ld4.8b { v0, v1, v2, v3 }, [x0], #32 -# CHECK: ld4.16b { v0, v1, v2, v3 }, [x0], #64 -# CHECK: ld4.4h { v0, v1, v2, v3 }, [x0], #32 -# CHECK: ld4.8h { v0, v1, v2, v3 }, [x0], #64 -# CHECK: ld4.2s { v0, v1, v2, v3 }, [x0], #32 -# CHECK: ld4.4s { v0, v1, v2, v3 }, [x0], #64 -# CHECK: ld4.2d { v0, v1, v2, v3 }, [x0], #64 - -0x00 0x00 0x9f 0x0c -0x00 0x00 0x9f 0x4c -0x00 0x04 0x9f 0x0c -0x00 0x04 0x9f 0x4c -0x00 0x08 0x9f 0x0c -0x00 0x08 0x9f 0x4c -0x00 0x0c 0x9f 0x4c - -# CHECK: st4.8b { v0, v1, v2, v3 }, [x0], #32 -# CHECK: st4.16b { v0, v1, v2, v3 }, [x0], #64 -# CHECK: st4.4h { v0, v1, v2, v3 }, [x0], #32 -# CHECK: st4.8h { v0, v1, v2, v3 }, [x0], #64 -# CHECK: st4.2s { v0, v1, v2, v3 }, [x0], #32 -# CHECK: st4.4s { v0, v1, v2, v3 }, [x0], #64 -# CHECK: st4.2d { v0, v1, v2, v3 }, [x0], #64 - -0x41 0x00 0x83 0x0c -0x42 0x00 0x84 0x4c -0x64 0x04 0x85 0x0c -0x87 0x04 0x86 0x4c -0x0c 0x08 0x87 0x0c -0x0a 0x08 0x88 0x4c -0x4f 0x0c 0x8a 0x4c - -# CHECK: st4.8b { v1, v2, v3, v4 }, [x2], x3 -# CHECK: st4.16b { v2, v3, v4, v5 }, [x2], x4 -# CHECK: st4.4h { v4, v5, v6, v7 }, [x3], x5 -# CHECK: st4.8h { v7, v8, v9, v10 }, [x4], x6 -# CHECK: st4.2s { v12, v13, v14, v15 }, [x0], x7 -# CHECK: st4.4s { v10, v11, v12, v13 }, [x0], x8 -# CHECK: st4.2d { v15, v16, v17, v18 }, [x2], x10 - -0x61 0x28 0x60 0x0d -0x82 0xa4 0x60 0x4d -0xc3 0x70 0x60 0x0d -0xe4 0xb0 0x60 0x4d - -# CHECK: ld4.b { v1, v2, v3, v4 }[2], [x3] -# CHECK: ld4.d { v2, v3, v4, v5 }[1], [x4] -# CHECK: ld4.h { v3, v4, v5, v6 }[2], [x6] -# CHECK: ld4.s { v4, v5, v6, v7 }[3], [x7] - -0x61 0x28 0x20 0x0d -0x82 0xa4 0x20 0x4d -0xc3 0x70 0x20 0x0d -0xe4 0xb0 0x20 0x4d - -# CHECK: st4.b { v1, v2, v3, v4 }[2], [x3] -# CHECK: st4.d { v2, v3, v4, v5 }[1], [x4] -# CHECK: st4.h { v3, v4, v5, v6 }[2], [x6] -# CHECK: st4.s { v4, v5, v6, v7 }[3], [x7] - -0x21 0xe0 0x60 0x0d -0x21 0xe0 0xe2 0x0d -0x21 0xe0 0x60 0x4d -0x21 0xe0 0xe2 0x4d -0x21 0xe4 0x60 0x0d -0x21 0xe4 0xe2 0x0d -0x21 0xe4 0x60 0x4d -0x21 0xe4 0xe2 0x4d -0x21 0xe8 0x60 0x0d -0x21 0xe8 0xe2 0x0d -0x21 0xec 0x60 0x4d -0x21 0xec 0xe2 0x4d -0x21 0xec 0x60 0x0d -0x21 0xec 0xe2 0x0d - -# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1] -# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], x2 -# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1] -# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], x2 -# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1] -# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], x2 -# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1] -# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], x2 -# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1] -# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], x2 -# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1] -# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], x2 -# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1] -# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], x2 - -0x21 0xe0 0xff 0x0d -0x21 0xe0 0xff 0x4d -0x21 0xe4 0xff 0x0d -0x21 0xe4 0xff 0x4d -0x21 0xe8 0xff 0x0d -0x21 0xec 0xff 0x4d -0x21 0xec 0xff 0x0d - -# CHECK: ld4r.8b { v1, v2, v3, v4 }, [x1], #4 -# CHECK: ld4r.16b { v1, v2, v3, v4 }, [x1], #4 -# CHECK: ld4r.4h { v1, v2, v3, v4 }, [x1], #8 -# CHECK: ld4r.8h { v1, v2, v3, v4 }, [x1], #8 -# CHECK: ld4r.2s { v1, v2, v3, v4 }, [x1], #16 -# CHECK: ld4r.2d { v1, v2, v3, v4 }, [x1], #32 -# CHECK: ld4r.1d { v1, v2, v3, v4 }, [x1], #32 - -0x20 0xe4 0x00 0x2f -0x20 0xe4 0x00 0x6f -0x20 0xe4 0x00 0x0f -0x20 0xe4 0x00 0x4f - -# CHECK: movi d0, #0x000000000000ff -# CHECK: movi.2d v0, #0x000000000000ff -# CHECK: movi.8b v0, #0x1 -# CHECK: movi.16b v0, #0x1 - -0x20 0x04 0x00 0x0f -0x20 0x24 0x00 0x0f -0x20 0x44 0x00 0x0f -0x20 0x64 0x00 0x0f - -# CHECK: movi.2s v0, #0x1 -# CHECK: movi.2s v0, #0x1, lsl #8 -# CHECK: movi.2s v0, #0x1, lsl #16 -# CHECK: movi.2s v0, #0x1, lsl #24 - -0x20 0x04 0x00 0x4f -0x20 0x24 0x00 0x4f -0x20 0x44 0x00 0x4f -0x20 0x64 0x00 0x4f - -# CHECK: movi.4s v0, #0x1 -# CHECK: movi.4s v0, #0x1, lsl #8 -# CHECK: movi.4s v0, #0x1, lsl #16 -# CHECK: movi.4s v0, #0x1, lsl #24 - -0x20 0x84 0x00 0x0f -0x20 0xa4 0x00 0x0f - -# CHECK: movi.4h v0, #0x1 -# CHECK: movi.4h v0, #0x1, lsl #8 - -0x20 0x84 0x00 0x4f -0x20 0xa4 0x00 0x4f - -# CHECK: movi.8h v0, #0x1 -# CHECK: movi.8h v0, #0x1, lsl #8 - -0x20 0x04 0x00 0x2f -0x20 0x24 0x00 0x2f -0x20 0x44 0x00 0x2f -0x20 0x64 0x00 0x2f - -# CHECK: mvni.2s v0, #0x1 -# CHECK: mvni.2s v0, #0x1, lsl #8 -# CHECK: mvni.2s v0, #0x1, lsl #16 -# CHECK: mvni.2s v0, #0x1, lsl #24 - -0x20 0x04 0x00 0x6f -0x20 0x24 0x00 0x6f -0x20 0x44 0x00 0x6f -0x20 0x64 0x00 0x6f - -# CHECK: mvni.4s v0, #0x1 -# CHECK: mvni.4s v0, #0x1, lsl #8 -# CHECK: mvni.4s v0, #0x1, lsl #16 -# CHECK: mvni.4s v0, #0x1, lsl #24 - -0x20 0x84 0x00 0x2f -0x20 0xa4 0x00 0x2f - -# CHECK: mvni.4h v0, #0x1 -# CHECK: mvni.4h v0, #0x1, lsl #8 - -0x20 0x84 0x00 0x6f -0x20 0xa4 0x00 0x6f - -# CHECK: mvni.8h v0, #0x1 -# CHECK: mvni.8h v0, #0x1, lsl #8 - -0x20 0xc4 0x00 0x2f -0x20 0xd4 0x00 0x2f -0x20 0xc4 0x00 0x6f -0x20 0xd4 0x00 0x6f - -# CHECK: mvni.2s v0, #0x1, msl #8 -# CHECK: mvni.2s v0, #0x1, msl #16 -# CHECK: mvni.4s v0, #0x1, msl #8 -# CHECK: mvni.4s v0, #0x1, msl #16 - -0x00 0x88 0x21 0x2e -0x00 0x98 0x21 0x2e -0x00 0x98 0xa1 0x2e -0x00 0x98 0x21 0x0e -0x00 0x88 0x21 0x0e -0x00 0x88 0xa1 0x0e -0x00 0x98 0xa1 0x0e - -# CHECK: frinta.2s v0, v0 -# CHECK: frintx.2s v0, v0 -# CHECK: frinti.2s v0, v0 -# CHECK: frintm.2s v0, v0 -# CHECK: frintn.2s v0, v0 -# CHECK: frintp.2s v0, v0 -# CHECK: frintz.2s v0, v0 - -#===-------------------------------------------------------------------------=== -# AdvSIMD scalar x index instructions -#===-------------------------------------------------------------------------=== - -0x00 0x18 0xa0 0x5f -0x00 0x18 0xc0 0x5f -0x00 0x58 0xa0 0x5f -0x00 0x58 0xc0 0x5f -0x00 0x98 0xa0 0x7f -0x00 0x98 0xc0 0x7f -0x00 0x98 0xa0 0x5f -0x00 0x98 0xc0 0x5f -0x00 0x38 0x70 0x5f -0x00 0x38 0xa0 0x5f -0x00 0x78 0x70 0x5f -0x00 0xc8 0x70 0x5f -0x00 0xc8 0xa0 0x5f -0x00 0xb8 0x70 0x5f -0x00 0xb8 0xa0 0x5f -0x00 0xd8 0x70 0x5f -0x00 0xd8 0xa0 0x5f - -# CHECK: fmla.s s0, s0, v0[3] -# CHECK: fmla.d d0, d0, v0[1] -# CHECK: fmls.s s0, s0, v0[3] -# CHECK: fmls.d d0, d0, v0[1] -# CHECK: fmulx.s s0, s0, v0[3] -# CHECK: fmulx.d d0, d0, v0[1] -# CHECK: fmul.s s0, s0, v0[3] -# CHECK: fmul.d d0, d0, v0[1] -# CHECK: sqdmlal.h s0, h0, v0[7] -# CHECK: sqdmlal.s d0, s0, v0[3] -# CHECK: sqdmlsl.h s0, h0, v0[7] -# CHECK: sqdmulh.h h0, h0, v0[7] -# CHECK: sqdmulh.s s0, s0, v0[3] -# CHECK: sqdmull.h s0, h0, v0[7] -# CHECK: sqdmull.s d0, s0, v0[3] -# CHECK: sqrdmulh.h h0, h0, v0[7] -# CHECK: sqrdmulh.s s0, s0, v0[3] - -#===-------------------------------------------------------------------------=== -# AdvSIMD vector x index instructions -#===-------------------------------------------------------------------------=== - - 0x00 0x10 0x80 0x0f - 0x00 0x10 0xa0 0x4f - 0x00 0x18 0xc0 0x4f - 0x00 0x50 0x80 0x0f - 0x00 0x50 0xa0 0x4f - 0x00 0x58 0xc0 0x4f - 0x00 0x90 0x80 0x2f - 0x00 0x90 0xa0 0x6f - 0x00 0x98 0xc0 0x6f - 0x00 0x90 0x80 0x0f - 0x00 0x90 0xa0 0x4f - 0x00 0x98 0xc0 0x4f - 0x00 0x00 0x40 0x2f - 0x00 0x00 0x50 0x6f - 0x00 0x08 0x80 0x2f - 0x00 0x08 0xa0 0x6f - 0x00 0x40 0x40 0x2f - 0x00 0x40 0x50 0x6f - 0x00 0x48 0x80 0x2f - 0x00 0x48 0xa0 0x6f - 0x00 0x80 0x40 0x0f - 0x00 0x80 0x50 0x4f - 0x00 0x88 0x80 0x0f - 0x00 0x88 0xa0 0x4f - 0x00 0x20 0x40 0x0f - 0x00 0x20 0x50 0x4f - 0x00 0x28 0x80 0x0f - 0x00 0x28 0xa0 0x4f - 0x00 0x60 0x40 0x0f - 0x00 0x60 0x50 0x4f - 0x00 0x68 0x80 0x0f - 0x00 0x68 0xa0 0x4f - 0x00 0xa0 0x40 0x0f - 0x00 0xa0 0x50 0x4f - 0x00 0xa8 0x80 0x0f - 0x00 0xa8 0xa0 0x4f - 0x00 0x30 0x40 0x0f - 0x00 0x30 0x50 0x4f - 0x00 0x38 0x80 0x0f - 0x00 0x38 0xa0 0x4f - 0x00 0x70 0x40 0x0f - 0x00 0x70 0x50 0x4f - 0x00 0x78 0x80 0x0f - 0x00 0x78 0xa0 0x4f - 0x00 0xc0 0x40 0x0f - 0x00 0xc0 0x50 0x4f - 0x00 0xc8 0x80 0x0f - 0x00 0xc8 0xa0 0x4f - 0x00 0xb0 0x40 0x0f - 0x00 0xb0 0x50 0x4f - 0x00 0xb8 0x80 0x0f - 0x00 0xb8 0xa0 0x4f - 0x00 0xd0 0x40 0x0f - 0x00 0xd0 0x50 0x4f - 0x00 0xd8 0x80 0x0f - 0x00 0xd8 0xa0 0x4f - 0x00 0x20 0x40 0x2f - 0x00 0x20 0x50 0x6f - 0x00 0x28 0x80 0x2f - 0x00 0x28 0xa0 0x6f - 0x00 0x60 0x40 0x2f - 0x00 0x60 0x50 0x6f - 0x00 0x68 0x80 0x2f - 0x00 0x68 0xa0 0x6f - 0x00 0xa0 0x40 0x2f - 0x00 0xa0 0x50 0x6f - 0x00 0xa8 0x80 0x2f - 0x00 0xa8 0xa0 0x6f - -# CHECK: fmla.2s v0, v0, v0[0] -# CHECK: fmla.4s v0, v0, v0[1] -# CHECK: fmla.2d v0, v0, v0[1] -# CHECK: fmls.2s v0, v0, v0[0] -# CHECK: fmls.4s v0, v0, v0[1] -# CHECK: fmls.2d v0, v0, v0[1] -# CHECK: fmulx.2s v0, v0, v0[0] -# CHECK: fmulx.4s v0, v0, v0[1] -# CHECK: fmulx.2d v0, v0, v0[1] -# CHECK: fmul.2s v0, v0, v0[0] -# CHECK: fmul.4s v0, v0, v0[1] -# CHECK: fmul.2d v0, v0, v0[1] -# CHECK: mla.4h v0, v0, v0[0] -# CHECK: mla.8h v0, v0, v0[1] -# CHECK: mla.2s v0, v0, v0[2] -# CHECK: mla.4s v0, v0, v0[3] -# CHECK: mls.4h v0, v0, v0[0] -# CHECK: mls.8h v0, v0, v0[1] -# CHECK: mls.2s v0, v0, v0[2] -# CHECK: mls.4s v0, v0, v0[3] -# CHECK: mul.4h v0, v0, v0[0] -# CHECK: mul.8h v0, v0, v0[1] -# CHECK: mul.2s v0, v0, v0[2] -# CHECK: mul.4s v0, v0, v0[3] -# CHECK: smlal.4s v0, v0, v0[0] -# CHECK: smlal2.4s v0, v0, v0[1] -# CHECK: smlal.2d v0, v0, v0[2] -# CHECK: smlal2.2d v0, v0, v0[3] -# CHECK: smlsl.4s v0, v0, v0[0] -# CHECK: smlsl2.4s v0, v0, v0[1] -# CHECK: smlsl.2d v0, v0, v0[2] -# CHECK: smlsl2.2d v0, v0, v0[3] -# CHECK: smull.4s v0, v0, v0[0] -# CHECK: smull2.4s v0, v0, v0[1] -# CHECK: smull.2d v0, v0, v0[2] -# CHECK: smull2.2d v0, v0, v0[3] -# CHECK: sqdmlal.4s v0, v0, v0[0] -# CHECK: sqdmlal2.4s v0, v0, v0[1] -# CHECK: sqdmlal.2d v0, v0, v0[2] -# CHECK: sqdmlal2.2d v0, v0, v0[3] -# CHECK: sqdmlsl.4s v0, v0, v0[0] -# CHECK: sqdmlsl2.4s v0, v0, v0[1] -# CHECK: sqdmlsl.2d v0, v0, v0[2] -# CHECK: sqdmlsl2.2d v0, v0, v0[3] -# CHECK: sqdmulh.4h v0, v0, v0[0] -# CHECK: sqdmulh.8h v0, v0, v0[1] -# CHECK: sqdmulh.2s v0, v0, v0[2] -# CHECK: sqdmulh.4s v0, v0, v0[3] -# CHECK: sqdmull.4s v0, v0, v0[0] -# CHECK: sqdmull2.4s v0, v0, v0[1] -# CHECK: sqdmull.2d v0, v0, v0[2] -# CHECK: sqdmull2.2d v0, v0, v0[3] -# CHECK: sqrdmulh.4h v0, v0, v0[0] -# CHECK: sqrdmulh.8h v0, v0, v0[1] -# CHECK: sqrdmulh.2s v0, v0, v0[2] -# CHECK: sqrdmulh.4s v0, v0, v0[3] -# CHECK: umlal.4s v0, v0, v0[0] -# CHECK: umlal2.4s v0, v0, v0[1] -# CHECK: umlal.2d v0, v0, v0[2] -# CHECK: umlal2.2d v0, v0, v0[3] -# CHECK: umlsl.4s v0, v0, v0[0] -# CHECK: umlsl2.4s v0, v0, v0[1] -# CHECK: umlsl.2d v0, v0, v0[2] -# CHECK: umlsl2.2d v0, v0, v0[3] -# CHECK: umull.4s v0, v0, v0[0] -# CHECK: umull2.4s v0, v0, v0[1] -# CHECK: umull.2d v0, v0, v0[2] -# CHECK: umull2.2d v0, v0, v0[3] - - -#===-------------------------------------------------------------------------=== -# AdvSIMD scalar + shift instructions -#===-------------------------------------------------------------------------=== - - 0x00 0x54 0x41 0x5f - 0x00 0x54 0x41 0x7f - 0x00 0x9c 0x09 0x5f - 0x00 0x9c 0x12 0x5f - 0x00 0x9c 0x23 0x5f - 0x00 0x8c 0x09 0x7f - 0x00 0x8c 0x12 0x7f - 0x00 0x8c 0x23 0x7f - 0x00 0x64 0x09 0x7f - 0x00 0x64 0x12 0x7f - 0x00 0x64 0x23 0x7f - 0x00 0x64 0x44 0x7f - 0x00 0x74 0x09 0x5f - 0x00 0x74 0x12 0x5f - 0x00 0x74 0x23 0x5f - 0x00 0x74 0x44 0x5f - 0x00 0x94 0x09 0x5f - 0x00 0x94 0x12 0x5f - 0x00 0x94 0x23 0x5f - 0x00 0x84 0x09 0x7f - 0x00 0x84 0x12 0x7f - 0x00 0x84 0x23 0x7f - 0x00 0x44 0x41 0x7f - 0x00 0x24 0x41 0x5f - 0x00 0x34 0x41 0x5f - 0x00 0x04 0x41 0x5f - 0x00 0xe4 0x21 0x7f - 0x00 0xe4 0x42 0x7f - 0x00 0x9c 0x09 0x7f - 0x00 0x9c 0x12 0x7f - 0x00 0x9c 0x23 0x7f - 0x00 0x74 0x09 0x7f - 0x00 0x74 0x12 0x7f - 0x00 0x74 0x23 0x7f - 0x00 0x74 0x44 0x7f - 0x00 0x94 0x09 0x7f - 0x00 0x94 0x12 0x7f - 0x00 0x94 0x23 0x7f - 0x00 0x24 0x41 0x7f - 0x00 0x34 0x41 0x7f - 0x00 0x04 0x41 0x7f - 0x00 0x14 0x41 0x7f - -# CHECK: shl d0, d0, #1 -# CHECK: sli d0, d0, #1 -# CHECK: sqrshrn b0, h0, #7 -# CHECK: sqrshrn h0, s0, #14 -# CHECK: sqrshrn s0, d0, #29 -# CHECK: sqrshrun b0, h0, #7 -# CHECK: sqrshrun h0, s0, #14 -# CHECK: sqrshrun s0, d0, #29 -# CHECK: sqshlu b0, b0, #1 -# CHECK: sqshlu h0, h0, #2 -# CHECK: sqshlu s0, s0, #3 -# CHECK: sqshlu d0, d0, #4 -# CHECK: sqshl b0, b0, #1 -# CHECK: sqshl h0, h0, #2 -# CHECK: sqshl s0, s0, #3 -# CHECK: sqshl d0, d0, #4 -# CHECK: sqshrn b0, h0, #7 -# CHECK: sqshrn h0, s0, #14 -# CHECK: sqshrn s0, d0, #29 -# CHECK: sqshrun b0, h0, #7 -# CHECK: sqshrun h0, s0, #14 -# CHECK: sqshrun s0, d0, #29 -# CHECK: sri d0, d0, #63 -# CHECK: srshr d0, d0, #63 -# CHECK: srsra d0, d0, #63 -# CHECK: sshr d0, d0, #63 -# CHECK: ucvtf s0, s0, #31 -# CHECK: ucvtf d0, d0, #62 -# CHECK: uqrshrn b0, h0, #7 -# CHECK: uqrshrn h0, s0, #14 -# CHECK: uqrshrn s0, d0, #29 -# CHECK: uqshl b0, b0, #1 -# CHECK: uqshl h0, h0, #2 -# CHECK: uqshl s0, s0, #3 -# CHECK: uqshl d0, d0, #4 -# CHECK: uqshrn b0, h0, #7 -# CHECK: uqshrn h0, s0, #14 -# CHECK: uqshrn s0, d0, #29 -# CHECK: urshr d0, d0, #63 -# CHECK: ursra d0, d0, #63 -# CHECK: ushr d0, d0, #63 -# CHECK: usra d0, d0, #63 - -#===-------------------------------------------------------------------------=== -# AdvSIMD vector + shift instructions -#===-------------------------------------------------------------------------=== - - 0x00 0xfc 0x21 0x0f - 0x00 0xfc 0x22 0x4f - 0x00 0xfc 0x43 0x4f - 0x00 0xfc 0x21 0x2f - 0x00 0xfc 0x22 0x6f - 0x00 0xfc 0x43 0x6f - 0x00 0x8c 0x09 0x0f - 0x00 0x8c 0x0a 0x4f - 0x00 0x8c 0x13 0x0f - 0x00 0x8c 0x14 0x4f - 0x00 0x8c 0x25 0x0f - 0x00 0x8c 0x26 0x4f - 0x00 0xe4 0x21 0x0f - 0x00 0xe4 0x22 0x4f - 0x00 0xe4 0x43 0x4f - 0x00 0x54 0x09 0x0f - 0x00 0x54 0x0a 0x4f - 0x00 0x54 0x13 0x0f - 0x00 0x54 0x14 0x4f - 0x00 0x54 0x25 0x0f - 0x00 0x54 0x26 0x4f - 0x00 0x54 0x47 0x4f - 0x00 0x84 0x09 0x0f - 0x00 0x84 0x0a 0x4f - 0x00 0x84 0x13 0x0f - 0x00 0x84 0x14 0x4f - 0x00 0x84 0x25 0x0f - 0x00 0x84 0x26 0x4f - 0x00 0x54 0x09 0x2f - 0x00 0x54 0x0a 0x6f - 0x00 0x54 0x13 0x2f - 0x00 0x54 0x14 0x6f - 0x00 0x54 0x25 0x2f - 0x00 0x54 0x26 0x6f - 0x00 0x54 0x47 0x6f - 0x00 0x9c 0x09 0x0f - 0x00 0x9c 0x0a 0x4f - 0x00 0x9c 0x13 0x0f - 0x00 0x9c 0x14 0x4f - 0x00 0x9c 0x25 0x0f - 0x00 0x9c 0x26 0x4f - 0x00 0x8c 0x09 0x2f - 0x00 0x8c 0x0a 0x6f - 0x00 0x8c 0x13 0x2f - 0x00 0x8c 0x14 0x6f - 0x00 0x8c 0x25 0x2f - 0x00 0x8c 0x26 0x6f - 0x00 0x64 0x09 0x2f - 0x00 0x64 0x0a 0x6f - 0x00 0x64 0x13 0x2f - 0x00 0x64 0x14 0x6f - 0x00 0x64 0x25 0x2f - 0x00 0x64 0x26 0x6f - 0x00 0x64 0x47 0x6f - 0x00 0x74 0x09 0x0f - 0x00 0x74 0x0a 0x4f - 0x00 0x74 0x13 0x0f - 0x00 0x74 0x14 0x4f - 0x00 0x74 0x25 0x0f - 0x00 0x74 0x26 0x4f - 0x00 0x74 0x47 0x4f - 0x00 0x94 0x09 0x0f - 0x00 0x94 0x0a 0x4f - 0x00 0x94 0x13 0x0f - 0x00 0x94 0x14 0x4f - 0x00 0x94 0x25 0x0f - 0x00 0x94 0x26 0x4f - 0x00 0x84 0x09 0x2f - 0x00 0x84 0x0a 0x6f - 0x00 0x84 0x13 0x2f - 0x00 0x84 0x14 0x6f - 0x00 0x84 0x25 0x2f - 0x00 0x84 0x26 0x6f - 0x00 0x44 0x09 0x2f - 0x00 0x44 0x0a 0x6f - 0x00 0x44 0x13 0x2f - 0x00 0x44 0x14 0x6f - 0x00 0x44 0x25 0x2f - 0x00 0x44 0x26 0x6f - 0x00 0x44 0x47 0x6f - 0x00 0x24 0x09 0x0f - 0x00 0x24 0x0a 0x4f - 0x00 0x24 0x13 0x0f - 0x00 0x24 0x14 0x4f - 0x00 0x24 0x25 0x0f - 0x00 0x24 0x26 0x4f - 0x00 0x24 0x47 0x4f - 0x00 0x34 0x09 0x0f - 0x00 0x34 0x0a 0x4f - 0x00 0x34 0x13 0x0f - 0x00 0x34 0x14 0x4f - 0x00 0x34 0x25 0x0f - 0x00 0x34 0x26 0x4f - 0x00 0x34 0x47 0x4f - 0x00 0xa4 0x09 0x0f - 0x00 0xa4 0x0a 0x4f - 0x00 0xa4 0x13 0x0f - 0x00 0xa4 0x14 0x4f - 0x00 0xa4 0x25 0x0f - 0x00 0xa4 0x26 0x4f - 0x00 0x04 0x09 0x0f - 0x00 0x04 0x0a 0x4f - 0x00 0x04 0x13 0x0f - 0x00 0x04 0x14 0x4f - 0x00 0x04 0x25 0x0f - 0x00 0x04 0x26 0x4f - 0x00 0x04 0x47 0x4f - 0x00 0x04 0x09 0x0f - 0x00 0x14 0x0a 0x4f - 0x00 0x14 0x13 0x0f - 0x00 0x14 0x14 0x4f - 0x00 0x14 0x25 0x0f - 0x00 0x14 0x26 0x4f - 0x00 0x14 0x47 0x4f - 0x00 0x14 0x40 0x5f - 0x00 0xe4 0x21 0x2f - 0x00 0xe4 0x22 0x6f - 0x00 0xe4 0x43 0x6f - 0x00 0x9c 0x09 0x2f - 0x00 0x9c 0x0a 0x6f - 0x00 0x9c 0x13 0x2f - 0x00 0x9c 0x14 0x6f - 0x00 0x9c 0x25 0x2f - 0x00 0x9c 0x26 0x6f - 0x00 0x74 0x09 0x2f - 0x00 0x74 0x0a 0x6f - 0x00 0x74 0x13 0x2f - 0x00 0x74 0x14 0x6f - 0x00 0x74 0x25 0x2f - 0x00 0x74 0x26 0x6f - 0x00 0x74 0x47 0x6f - 0x00 0x94 0x09 0x2f - 0x00 0x94 0x0a 0x6f - 0x00 0x94 0x13 0x2f - 0x00 0x94 0x14 0x6f - 0x00 0x94 0x25 0x2f - 0x00 0x94 0x26 0x6f - 0x00 0x24 0x09 0x2f - 0x00 0x24 0x0a 0x6f - 0x00 0x24 0x13 0x2f - 0x00 0x24 0x14 0x6f - 0x00 0x24 0x25 0x2f - 0x00 0x24 0x26 0x6f - 0x00 0x24 0x47 0x6f - 0x00 0x34 0x09 0x2f - 0x00 0x34 0x0a 0x6f - 0x00 0x34 0x13 0x2f - 0x00 0x34 0x14 0x6f - 0x00 0x34 0x25 0x2f - 0x00 0x34 0x26 0x6f - 0x00 0x34 0x47 0x6f - 0x00 0xa4 0x09 0x2f - 0x00 0xa4 0x0a 0x6f - 0x00 0xa4 0x13 0x2f - 0x00 0xa4 0x14 0x6f - 0x00 0xa4 0x25 0x2f - 0x00 0xa4 0x26 0x6f - 0x00 0x04 0x09 0x2f - 0x00 0x04 0x0a 0x6f - 0x00 0x04 0x13 0x2f - 0x00 0x04 0x14 0x6f - 0x00 0x04 0x25 0x2f - 0x00 0x04 0x26 0x6f - 0x00 0x04 0x47 0x6f - 0x00 0x14 0x09 0x2f - 0x00 0x14 0x0a 0x6f - 0x00 0x14 0x13 0x2f - 0x00 0x14 0x14 0x6f - 0x00 0x14 0x25 0x2f - 0x00 0x14 0x26 0x6f - 0x00 0x14 0x47 0x6f - -# CHECK: fcvtzs.2s v0, v0, #31 -# CHECK: fcvtzs.4s v0, v0, #30 -# CHECK: fcvtzs.2d v0, v0, #61 -# CHECK: fcvtzu.2s v0, v0, #31 -# CHECK: fcvtzu.4s v0, v0, #30 -# CHECK: fcvtzu.2d v0, v0, #61 -# CHECK: rshrn.8b v0, v0, #7 -# CHECK: rshrn2.16b v0, v0, #6 -# CHECK: rshrn.4h v0, v0, #13 -# CHECK: rshrn2.8h v0, v0, #12 -# CHECK: rshrn.2s v0, v0, #27 -# CHECK: rshrn2.4s v0, v0, #26 -# CHECK: scvtf.2s v0, v0, #31 -# CHECK: scvtf.4s v0, v0, #30 -# CHECK: scvtf.2d v0, v0, #61 -# CHECK: shl.8b v0, v0, #1 -# CHECK: shl.16b v0, v0, #2 -# CHECK: shl.4h v0, v0, #3 -# CHECK: shl.8h v0, v0, #4 -# CHECK: shl.2s v0, v0, #5 -# CHECK: shl.4s v0, v0, #6 -# CHECK: shl.2d v0, v0, #7 -# CHECK: shrn.8b v0, v0, #7 -# CHECK: shrn2.16b v0, v0, #6 -# CHECK: shrn.4h v0, v0, #13 -# CHECK: shrn2.8h v0, v0, #12 -# CHECK: shrn.2s v0, v0, #27 -# CHECK: shrn2.4s v0, v0, #26 -# CHECK: sli.8b v0, v0, #1 -# CHECK: sli.16b v0, v0, #2 -# CHECK: sli.4h v0, v0, #3 -# CHECK: sli.8h v0, v0, #4 -# CHECK: sli.2s v0, v0, #5 -# CHECK: sli.4s v0, v0, #6 -# CHECK: sli.2d v0, v0, #7 -# CHECK: sqrshrn.8b v0, v0, #7 -# CHECK: sqrshrn2.16b v0, v0, #6 -# CHECK: sqrshrn.4h v0, v0, #13 -# CHECK: sqrshrn2.8h v0, v0, #12 -# CHECK: sqrshrn.2s v0, v0, #27 -# CHECK: sqrshrn2.4s v0, v0, #26 -# CHECK: sqrshrun.8b v0, v0, #7 -# CHECK: sqrshrun2.16b v0, v0, #6 -# CHECK: sqrshrun.4h v0, v0, #13 -# CHECK: sqrshrun2.8h v0, v0, #12 -# CHECK: sqrshrun.2s v0, v0, #27 -# CHECK: sqrshrun2.4s v0, v0, #26 -# CHECK: sqshlu.8b v0, v0, #1 -# CHECK: sqshlu.16b v0, v0, #2 -# CHECK: sqshlu.4h v0, v0, #3 -# CHECK: sqshlu.8h v0, v0, #4 -# CHECK: sqshlu.2s v0, v0, #5 -# CHECK: sqshlu.4s v0, v0, #6 -# CHECK: sqshlu.2d v0, v0, #7 -# CHECK: sqshl.8b v0, v0, #1 -# CHECK: sqshl.16b v0, v0, #2 -# CHECK: sqshl.4h v0, v0, #3 -# CHECK: sqshl.8h v0, v0, #4 -# CHECK: sqshl.2s v0, v0, #5 -# CHECK: sqshl.4s v0, v0, #6 -# CHECK: sqshl.2d v0, v0, #7 -# CHECK: sqshrn.8b v0, v0, #7 -# CHECK: sqshrn2.16b v0, v0, #6 -# CHECK: sqshrn.4h v0, v0, #13 -# CHECK: sqshrn2.8h v0, v0, #12 -# CHECK: sqshrn.2s v0, v0, #27 -# CHECK: sqshrn2.4s v0, v0, #26 -# CHECK: sqshrun.8b v0, v0, #7 -# CHECK: sqshrun2.16b v0, v0, #6 -# CHECK: sqshrun.4h v0, v0, #13 -# CHECK: sqshrun2.8h v0, v0, #12 -# CHECK: sqshrun.2s v0, v0, #27 -# CHECK: sqshrun2.4s v0, v0, #26 -# CHECK: sri.8b v0, v0, #7 -# CHECK: sri.16b v0, v0, #6 -# CHECK: sri.4h v0, v0, #13 -# CHECK: sri.8h v0, v0, #12 -# CHECK: sri.2s v0, v0, #27 -# CHECK: sri.4s v0, v0, #26 -# CHECK: sri.2d v0, v0, #57 -# CHECK: srshr.8b v0, v0, #7 -# CHECK: srshr.16b v0, v0, #6 -# CHECK: srshr.4h v0, v0, #13 -# CHECK: srshr.8h v0, v0, #12 -# CHECK: srshr.2s v0, v0, #27 -# CHECK: srshr.4s v0, v0, #26 -# CHECK: srshr.2d v0, v0, #57 -# CHECK: srsra.8b v0, v0, #7 -# CHECK: srsra.16b v0, v0, #6 -# CHECK: srsra.4h v0, v0, #13 -# CHECK: srsra.8h v0, v0, #12 -# CHECK: srsra.2s v0, v0, #27 -# CHECK: srsra.4s v0, v0, #26 -# CHECK: srsra.2d v0, v0, #57 -# CHECK: sshll.8h v0, v0, #1 -# CHECK: sshll2.8h v0, v0, #2 -# CHECK: sshll.4s v0, v0, #3 -# CHECK: sshll2.4s v0, v0, #4 -# CHECK: sshll.2d v0, v0, #5 -# CHECK: sshll2.2d v0, v0, #6 -# CHECK: sshr.8b v0, v0, #7 -# CHECK: sshr.16b v0, v0, #6 -# CHECK: sshr.4h v0, v0, #13 -# CHECK: sshr.8h v0, v0, #12 -# CHECK: sshr.2s v0, v0, #27 -# CHECK: sshr.4s v0, v0, #26 -# CHECK: sshr.2d v0, v0, #57 -# CHECK: sshr.8b v0, v0, #7 -# CHECK: ssra.16b v0, v0, #6 -# CHECK: ssra.4h v0, v0, #13 -# CHECK: ssra.8h v0, v0, #12 -# CHECK: ssra.2s v0, v0, #27 -# CHECK: ssra.4s v0, v0, #26 -# CHECK: ssra.2d v0, v0, #57 -# CHECK: ssra d0, d0, #64 -# CHECK: ucvtf.2s v0, v0, #31 -# CHECK: ucvtf.4s v0, v0, #30 -# CHECK: ucvtf.2d v0, v0, #61 -# CHECK: uqrshrn.8b v0, v0, #7 -# CHECK: uqrshrn2.16b v0, v0, #6 -# CHECK: uqrshrn.4h v0, v0, #13 -# CHECK: uqrshrn2.8h v0, v0, #12 -# CHECK: uqrshrn.2s v0, v0, #27 -# CHECK: uqrshrn2.4s v0, v0, #26 -# CHECK: uqshl.8b v0, v0, #1 -# CHECK: uqshl.16b v0, v0, #2 -# CHECK: uqshl.4h v0, v0, #3 -# CHECK: uqshl.8h v0, v0, #4 -# CHECK: uqshl.2s v0, v0, #5 -# CHECK: uqshl.4s v0, v0, #6 -# CHECK: uqshl.2d v0, v0, #7 -# CHECK: uqshrn.8b v0, v0, #7 -# CHECK: uqshrn2.16b v0, v0, #6 -# CHECK: uqshrn.4h v0, v0, #13 -# CHECK: uqshrn2.8h v0, v0, #12 -# CHECK: uqshrn.2s v0, v0, #27 -# CHECK: uqshrn2.4s v0, v0, #26 -# CHECK: urshr.8b v0, v0, #7 -# CHECK: urshr.16b v0, v0, #6 -# CHECK: urshr.4h v0, v0, #13 -# CHECK: urshr.8h v0, v0, #12 -# CHECK: urshr.2s v0, v0, #27 -# CHECK: urshr.4s v0, v0, #26 -# CHECK: urshr.2d v0, v0, #57 -# CHECK: ursra.8b v0, v0, #7 -# CHECK: ursra.16b v0, v0, #6 -# CHECK: ursra.4h v0, v0, #13 -# CHECK: ursra.8h v0, v0, #12 -# CHECK: ursra.2s v0, v0, #27 -# CHECK: ursra.4s v0, v0, #26 -# CHECK: ursra.2d v0, v0, #57 -# CHECK: ushll.8h v0, v0, #1 -# CHECK: ushll2.8h v0, v0, #2 -# CHECK: ushll.4s v0, v0, #3 -# CHECK: ushll2.4s v0, v0, #4 -# CHECK: ushll.2d v0, v0, #5 -# CHECK: ushll2.2d v0, v0, #6 -# CHECK: ushr.8b v0, v0, #7 -# CHECK: ushr.16b v0, v0, #6 -# CHECK: ushr.4h v0, v0, #13 -# CHECK: ushr.8h v0, v0, #12 -# CHECK: ushr.2s v0, v0, #27 -# CHECK: ushr.4s v0, v0, #26 -# CHECK: ushr.2d v0, v0, #57 -# CHECK: usra.8b v0, v0, #7 -# CHECK: usra.16b v0, v0, #6 -# CHECK: usra.4h v0, v0, #13 -# CHECK: usra.8h v0, v0, #12 -# CHECK: usra.2s v0, v0, #27 -# CHECK: usra.4s v0, v0, #26 -# CHECK: usra.2d v0, v0, #57 - - - 0x00 0xe0 0x20 0x0e - 0x00 0xe0 0x20 0x4e - 0x00 0xe0 0xe0 0x0e - 0x00 0xe0 0xe0 0x4e - -# CHECK: pmull.8h v0, v0, v0 -# CHECK: pmull2.8h v0, v0, v0 -# CHECK: pmull.1q v0, v0, v0 -# CHECK: pmull2.1q v0, v0, v0 - - 0x41 0xd8 0x70 0x7e - 0x83 0xd8 0x30 0x7e -# CHECK: faddp.2d d1, v2 -# CHECK: faddp.2s s3, v4 - - 0x82 0x60 0x01 0x4e - 0x80 0x60 0x01 0x0e - 0xa2 0x00 0x01 0x4e - 0xa0 0x00 0x01 0x0e - 0xa2 0x40 0x01 0x4e - 0xa0 0x40 0x01 0x0e - 0xc2 0x20 0x01 0x4e - 0xc0 0x20 0x01 0x0e - -# CHECK: tbl.16b v2, { v4, v5, v6, v7 }, v1 -# CHECK: tbl.8b v0, { v4, v5, v6, v7 }, v1 -# CHECK: tbl.16b v2, { v5 }, v1 -# CHECK: tbl.8b v0, { v5 }, v1 -# CHECK: tbl.16b v2, { v5, v6, v7 }, v1 -# CHECK: tbl.8b v0, { v5, v6, v7 }, v1 -# CHECK: tbl.16b v2, { v6, v7 }, v1 -# CHECK: tbl.8b v0, { v6, v7 }, v1 -# - 0x82 0x70 0x01 0x4e - 0x80 0x70 0x01 0x0e - 0xa2 0x10 0x01 0x4e - 0xa0 0x10 0x01 0x0e - 0xa2 0x50 0x01 0x4e - 0xa0 0x50 0x01 0x0e - 0xc2 0x30 0x01 0x4e - 0xc0 0x30 0x01 0x0e - -# CHECK: tbx.16b v2, { v4, v5, v6, v7 }, v1 -# CHECK: tbx.8b v0, { v4, v5, v6, v7 }, v1 -# CHECK: tbx.16b v2, { v5 }, v1 -# CHECK: tbx.8b v0, { v5 }, v1 -# CHECK: tbx.16b v2, { v5, v6, v7 }, v1 -# CHECK: tbx.8b v0, { v5, v6, v7 }, v1 -# CHECK: tbx.16b v2, { v6, v7 }, v1 -# CHECK: tbx.8b v0, { v6, v7 }, v1 -# - -0x00 0x80 0x20 0x0e -0x00 0x80 0x20 0x4e -0x00 0x80 0xa0 0x0e -0x00 0x80 0xa0 0x4e - -# CHECK: smlal.8h v0, v0, v0 -# CHECK: smlal2.8h v0, v0, v0 -# CHECK: smlal.2d v0, v0, v0 -# CHECK: smlal2.2d v0, v0, v0 - -0x00 0x80 0x20 0x2e -0x00 0x80 0x20 0x6e -0x00 0x80 0xa0 0x2e -0x00 0x80 0xa0 0x6e - -# CHECK: umlal.8h v0, v0, v0 -# CHECK: umlal2.8h v0, v0, v0 -# CHECK: umlal.2d v0, v0, v0 -# CHECK: umlal2.2d v0, v0, v0 - -0x00 0x90 0x60 0x5e -0x00 0x90 0xa0 0x5e -0x00 0xb0 0x60 0x5e -0x00 0xb0 0xa0 0x5e - -# CHECK: sqdmlal s0, h0, h0 -# CHECK: sqdmlal d0, s0, s0 -# CHECK: sqdmlsl s0, h0, h0 -# CHECK: sqdmlsl d0, s0, s0 - -0xaa 0xc5 0xc7 0x4d -0xaa 0xc9 0xc7 0x4d -0xaa 0xc1 0xc7 0x4d - -# CHECK: ld1r.8h { v10 }, [x13], x7 -# CHECK: ld1r.4s { v10 }, [x13], x7 -# CHECK: ld1r.16b { v10 }, [x13], x7 - -0x00 0xd0 0x60 0x5e -0x00 0xd0 0xa0 0x5e -# CHECK: sqdmull s0, h0, h0 -# CHECK: sqdmull d0, s0, s0 - -0x00 0xd8 0xa1 0x7e -0x00 0xd8 0xe1 0x7e - -# CHECK: frsqrte s0, s0 -# CHECK: frsqrte d0, d0 - -0xca 0xcd 0xc7 0x4d -0xea 0xc9 0xe7 0x4d -0xea 0xe9 0xc7 0x4d -0xea 0xe9 0xe7 0x4d -# CHECK: ld1r.2d { v10 }, [x14], x7 -# CHECK: ld2r.4s { v10, v11 }, [x15], x7 -# CHECK: ld3r.4s { v10, v11, v12 }, [x15], x7 -# CHECK: ld4r.4s { v10, v11, v12, v13 }, [x15], x7 - -#===-------------------------------------------------------------------------=== -# AdvSIMD scalar three same -#===-------------------------------------------------------------------------=== -0x62 0xdc 0x21 0x5e -# CHECK: fmulx s2, s3, s1 -0x62 0xdc 0x61 0x5e -# CHECK: fmulx d2, d3, d1 - - -# rdar://12511369 -0xe8 0x6b 0xdf 0x4c -# CHECK: ld1.4s { v8, v9, v10 }, [sp], #48 diff --git a/llvm/test/MC/Disassembler/ARM64/arithmetic.txt b/llvm/test/MC/Disassembler/ARM64/arithmetic.txt deleted file mode 100644 index bd870edc8af..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/arithmetic.txt +++ /dev/null @@ -1,526 +0,0 @@ -# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s - -#==---------------------------------------------------------------------------== -# Add/Subtract with carry/borrow -#==---------------------------------------------------------------------------== - -0x41 0x00 0x03 0x1a -0x41 0x00 0x03 0x9a -0x85 0x00 0x03 0x3a -0x85 0x00 0x03 0xba - -# CHECK: adc w1, w2, w3 -# CHECK: adc x1, x2, x3 -# CHECK: adcs w5, w4, w3 -# CHECK: adcs x5, x4, x3 - -0x41 0x00 0x03 0x5a -0x41 0x00 0x03 0xda -0x41 0x00 0x03 0x7a -0x41 0x00 0x03 0xfa - -# CHECK: sbc w1, w2, w3 -# CHECK: sbc x1, x2, x3 -# CHECK: sbcs w1, w2, w3 -# CHECK: sbcs x1, x2, x3 - -#==---------------------------------------------------------------------------== -# Add/Subtract with (optionally shifted) immediate -#==---------------------------------------------------------------------------== - -0x83 0x00 0x10 0x11 -0x83 0x00 0x10 0x91 - -# CHECK: add w3, w4, #1024 -# CHECK: add x3, x4, #1024 - -0x83 0x00 0x50 0x11 -0x83 0x00 0x40 0x11 -0x83 0x00 0x50 0x91 -0x83 0x00 0x40 0x91 -0xff 0x83 0x00 0x91 - -# CHECK: add w3, w4, #1024, lsl #12 -# CHECK: add x3, x4, #1024, lsl #12 -# CHECK: add x3, x4, #0, lsl #12 -# CHECK: add sp, sp, #32 - -0x83 0x00 0x10 0x31 -0x83 0x00 0x50 0x31 -0x83 0x00 0x10 0xb1 -0x83 0x00 0x50 0xb1 -0xff 0x83 0x00 0xb1 - -# CHECK: adds w3, w4, #1024 -# CHECK: adds w3, w4, #1024, lsl #12 -# CHECK: adds x3, x4, #1024 -# CHECK: adds x3, x4, #1024, lsl #12 -# CHECK: cmn sp, #32 - -0x83 0x00 0x10 0x51 -0x83 0x00 0x50 0x51 -0x83 0x00 0x10 0xd1 -0x83 0x00 0x50 0xd1 -0xff 0x83 0x00 0xd1 - -# CHECK: sub w3, w4, #1024 -# CHECK: sub w3, w4, #1024, lsl #12 -# CHECK: sub x3, x4, #1024 -# CHECK: sub x3, x4, #1024, lsl #12 -# CHECK: sub sp, sp, #32 - -0x83 0x00 0x10 0x71 -0x83 0x00 0x50 0x71 -0x83 0x00 0x10 0xf1 -0x83 0x00 0x50 0xf1 -0xff 0x83 0x00 0xf1 - -# CHECK: subs w3, w4, #1024 -# CHECK: subs w3, w4, #1024, lsl #12 -# CHECK: subs x3, x4, #1024 -# CHECK: subs x3, x4, #1024, lsl #12 -# CHECK: cmp sp, #32 - -#==---------------------------------------------------------------------------== -# Add/Subtract register with (optional) shift -#==---------------------------------------------------------------------------== - -0xac 0x01 0x0e 0x0b -0xac 0x01 0x0e 0x8b -0xac 0x31 0x0e 0x0b -0xac 0x31 0x0e 0x8b -0xac 0x29 0x4e 0x0b -0xac 0x29 0x4e 0x8b -0xac 0x1d 0x8e 0x0b -0xac 0x9d 0x8e 0x8b - -# CHECK: add w12, w13, w14 -# CHECK: add x12, x13, x14 -# CHECK: add w12, w13, w14, lsl #12 -# CHECK: add x12, x13, x14, lsl #12 -# CHECK: add w12, w13, w14, lsr #10 -# CHECK: add x12, x13, x14, lsr #10 -# CHECK: add w12, w13, w14, asr #7 -# CHECK: add x12, x13, x14, asr #39 - -0xac 0x01 0x0e 0x4b -0xac 0x01 0x0e 0xcb -0xac 0x31 0x0e 0x4b -0xac 0x31 0x0e 0xcb -0xac 0x29 0x4e 0x4b -0xac 0x29 0x4e 0xcb -0xac 0x1d 0x8e 0x4b -0xac 0x9d 0x8e 0xcb - -# CHECK: sub w12, w13, w14 -# CHECK: sub x12, x13, x14 -# CHECK: sub w12, w13, w14, lsl #12 -# CHECK: sub x12, x13, x14, lsl #12 -# CHECK: sub w12, w13, w14, lsr #10 -# CHECK: sub x12, x13, x14, lsr #10 -# CHECK: sub w12, w13, w14, asr #7 -# CHECK: sub x12, x13, x14, asr #39 - -0xac 0x01 0x0e 0x2b -0xac 0x01 0x0e 0xab -0xac 0x31 0x0e 0x2b -0xac 0x31 0x0e 0xab -0xac 0x29 0x4e 0x2b -0xac 0x29 0x4e 0xab -0xac 0x1d 0x8e 0x2b -0xac 0x9d 0x8e 0xab - -# CHECK: adds w12, w13, w14 -# CHECK: adds x12, x13, x14 -# CHECK: adds w12, w13, w14, lsl #12 -# CHECK: adds x12, x13, x14, lsl #12 -# CHECK: adds w12, w13, w14, lsr #10 -# CHECK: adds x12, x13, x14, lsr #10 -# CHECK: adds w12, w13, w14, asr #7 -# CHECK: adds x12, x13, x14, asr #39 - -0xac 0x01 0x0e 0x6b -0xac 0x01 0x0e 0xeb -0xac 0x31 0x0e 0x6b -0xac 0x31 0x0e 0xeb -0xac 0x29 0x4e 0x6b -0xac 0x29 0x4e 0xeb -0xac 0x1d 0x8e 0x6b -0xac 0x9d 0x8e 0xeb - -# CHECK: subs w12, w13, w14 -# CHECK: subs x12, x13, x14 -# CHECK: subs w12, w13, w14, lsl #12 -# CHECK: subs x12, x13, x14, lsl #12 -# CHECK: subs w12, w13, w14, lsr #10 -# CHECK: subs x12, x13, x14, lsr #10 -# CHECK: subs w12, w13, w14, asr #7 -# CHECK: subs x12, x13, x14, asr #39 - -#==---------------------------------------------------------------------------== -# Add/Subtract with (optional) extend -#==---------------------------------------------------------------------------== - -0x41 0x00 0x23 0x0b -0x41 0x20 0x23 0x0b -0x41 0x40 0x23 0x0b -0x41 0x60 0x23 0x0b -0x41 0x80 0x23 0x0b -0x41 0xa0 0x23 0x0b -0x41 0xc0 0x23 0x0b -0x41 0xe0 0x23 0x0b - -# CHECK: add w1, w2, w3, uxtb -# CHECK: add w1, w2, w3, uxth -# CHECK: add w1, w2, w3 -# CHECK: add w1, w2, w3, uxtx -# CHECK: add w1, w2, w3, sxtb -# CHECK: add w1, w2, w3, sxth -# CHECK: add w1, w2, w3, sxtw -# CHECK: add w1, w2, w3, sxtx - -0x41 0x00 0x23 0x8b -0x41 0x20 0x23 0x8b -0x41 0x40 0x23 0x8b -0x41 0x80 0x23 0x8b -0x41 0xa0 0x23 0x8b -0x41 0xc0 0x23 0x8b - -# CHECK: add x1, x2, w3, uxtb -# CHECK: add x1, x2, w3, uxth -# CHECK: add x1, x2, w3, uxtw -# CHECK: add x1, x2, w3, sxtb -# CHECK: add x1, x2, w3, sxth -# CHECK: add x1, x2, w3, sxtw - -0xe1 0x43 0x23 0x0b -0xe1 0x43 0x23 0x0b -0x5f 0x60 0x23 0x8b -0x5f 0x60 0x23 0x8b - -# CHECK: add w1, wsp, w3 -# CHECK: add w1, wsp, w3 -# CHECK: add sp, x2, x3 -# CHECK: add sp, x2, x3 - -0x41 0x00 0x23 0x4b -0x41 0x20 0x23 0x4b -0x41 0x40 0x23 0x4b -0x41 0x60 0x23 0x4b -0x41 0x80 0x23 0x4b -0x41 0xa0 0x23 0x4b -0x41 0xc0 0x23 0x4b -0x41 0xe0 0x23 0x4b - -# CHECK: sub w1, w2, w3, uxtb -# CHECK: sub w1, w2, w3, uxth -# CHECK: sub w1, w2, w3 -# CHECK: sub w1, w2, w3, uxtx -# CHECK: sub w1, w2, w3, sxtb -# CHECK: sub w1, w2, w3, sxth -# CHECK: sub w1, w2, w3, sxtw -# CHECK: sub w1, w2, w3, sxtx - -0x41 0x00 0x23 0xcb -0x41 0x20 0x23 0xcb -0x41 0x40 0x23 0xcb -0x41 0x80 0x23 0xcb -0x41 0xa0 0x23 0xcb -0x41 0xc0 0x23 0xcb - -# CHECK: sub x1, x2, w3, uxtb -# CHECK: sub x1, x2, w3, uxth -# CHECK: sub x1, x2, w3, uxtw -# CHECK: sub x1, x2, w3, sxtb -# CHECK: sub x1, x2, w3, sxth -# CHECK: sub x1, x2, w3, sxtw - -0xe1 0x43 0x23 0x4b -0xe1 0x43 0x23 0x4b -0x5f 0x60 0x23 0xcb -0x5f 0x60 0x23 0xcb - -# CHECK: sub w1, wsp, w3 -# CHECK: sub w1, wsp, w3 -# CHECK: sub sp, x2, x3 -# CHECK: sub sp, x2, x3 - -0x41 0x00 0x23 0x2b -0x41 0x20 0x23 0x2b -0x41 0x40 0x23 0x2b -0x41 0x60 0x23 0x2b -0x41 0x80 0x23 0x2b -0x41 0xa0 0x23 0x2b -0x41 0xc0 0x23 0x2b -0x41 0xe0 0x23 0x2b - -# CHECK: adds w1, w2, w3, uxtb -# CHECK: adds w1, w2, w3, uxth -# CHECK: adds w1, w2, w3 -# CHECK: adds w1, w2, w3, uxtx -# CHECK: adds w1, w2, w3, sxtb -# CHECK: adds w1, w2, w3, sxth -# CHECK: adds w1, w2, w3, sxtw -# CHECK: adds w1, w2, w3, sxtx - -0x41 0x00 0x23 0xab -0x41 0x20 0x23 0xab -0x41 0x40 0x23 0xab -0x41 0x80 0x23 0xab -0x41 0xa0 0x23 0xab -0x41 0xc0 0x23 0xab - -# CHECK: adds x1, x2, w3, uxtb -# CHECK: adds x1, x2, w3, uxth -# CHECK: adds x1, x2, w3, uxtw -# CHECK: adds x1, x2, w3, sxtb -# CHECK: adds x1, x2, w3, sxth -# CHECK: adds x1, x2, w3, sxtw - -0xe1 0x43 0x23 0x2b -0xe1 0x43 0x23 0x2b - -# CHECK: adds w1, wsp, w3 -# CHECK: adds w1, wsp, w3 - -0x41 0x00 0x23 0x6b -0x41 0x20 0x23 0x6b -0x41 0x40 0x23 0x6b -0x41 0x60 0x23 0x6b -0x41 0x80 0x23 0x6b -0x41 0xa0 0x23 0x6b -0x41 0xc0 0x23 0x6b -0x41 0xe0 0x23 0x6b - -# CHECK: subs w1, w2, w3, uxtb -# CHECK: subs w1, w2, w3, uxth -# CHECK: subs w1, w2, w3 -# CHECK: subs w1, w2, w3, uxtx -# CHECK: subs w1, w2, w3, sxtb -# CHECK: subs w1, w2, w3, sxth -# CHECK: subs w1, w2, w3, sxtw -# CHECK: subs w1, w2, w3, sxtx - -0x41 0x00 0x23 0xeb -0x41 0x20 0x23 0xeb -0x41 0x40 0x23 0xeb -0x41 0x80 0x23 0xeb -0x41 0xa0 0x23 0xeb -0x41 0xc0 0x23 0xeb - -# CHECK: subs x1, x2, w3, uxtb -# CHECK: subs x1, x2, w3, uxth -# CHECK: subs x1, x2, w3, uxtw -# CHECK: subs x1, x2, w3, sxtb -# CHECK: subs x1, x2, w3, sxth -# CHECK: subs x1, x2, w3, sxtw - -0xe1 0x43 0x23 0x6b -0xe1 0x43 0x23 0x6b - -# CHECK: subs w1, wsp, w3 -# CHECK: subs w1, wsp, w3 - -0x1f 0x41 0x28 0xeb -0x3f 0x41 0x28 0x6b -0xff 0x43 0x28 0x6b -0xff 0x43 0x28 0xeb - -# CHECK: cmp x8, w8, uxtw -# CHECK: cmp w9, w8, uxtw -# CHECK: cmp wsp, w8 -# CHECK: cmp sp, w8 - -0x3f 0x41 0x28 0x4b -0xe1 0x43 0x28 0x4b -0xff 0x43 0x28 0x4b -0x3f 0x41 0x28 0xcb -0xe1 0x43 0x28 0xcb -0xff 0x43 0x28 0xcb -0xe1 0x43 0x28 0x6b -0xe1 0x43 0x28 0xeb - -# CHECK: sub wsp, w9, w8 -# CHECK: sub w1, wsp, w8 -# CHECK: sub wsp, wsp, w8 -# CHECK: sub sp, x9, w8 -# CHECK: sub x1, sp, w8 -# CHECK: sub sp, sp, w8 -# CHECK: subs w1, wsp, w8 -# CHECK: subs x1, sp, w8 - -#==---------------------------------------------------------------------------== -# Signed/Unsigned divide -#==---------------------------------------------------------------------------== - -0x41 0x0c 0xc3 0x1a -0x41 0x0c 0xc3 0x9a -0x41 0x08 0xc3 0x1a -0x41 0x08 0xc3 0x9a - -# CHECK: sdiv w1, w2, w3 -# CHECK: sdiv x1, x2, x3 -# CHECK: udiv w1, w2, w3 -# CHECK: udiv x1, x2, x3 - -#==---------------------------------------------------------------------------== -# Variable shifts -#==---------------------------------------------------------------------------== - - 0x41 0x28 0xc3 0x1a -# CHECK: asr w1, w2, w3 - 0x41 0x28 0xc3 0x9a -# CHECK: asr x1, x2, x3 - 0x41 0x20 0xc3 0x1a -# CHECK: lsl w1, w2, w3 - 0x41 0x20 0xc3 0x9a -# CHECK: lsl x1, x2, x3 - 0x41 0x24 0xc3 0x1a -# CHECK: lsr w1, w2, w3 - 0x41 0x24 0xc3 0x9a -# CHECK: lsr x1, x2, x3 - 0x41 0x2c 0xc3 0x1a -# CHECK: ror w1, w2, w3 - 0x41 0x2c 0xc3 0x9a -# CHECK: ror x1, x2, x3 - -#==---------------------------------------------------------------------------== -# One operand instructions -#==---------------------------------------------------------------------------== - - 0x41 0x14 0xc0 0x5a -# CHECK: cls w1, w2 - 0x41 0x14 0xc0 0xda -# CHECK: cls x1, x2 - 0x41 0x10 0xc0 0x5a -# CHECK: clz w1, w2 - 0x41 0x10 0xc0 0xda -# CHECK: clz x1, x2 - 0x41 0x00 0xc0 0x5a -# CHECK: rbit w1, w2 - 0x41 0x00 0xc0 0xda -# CHECK: rbit x1, x2 - 0x41 0x08 0xc0 0x5a -# CHECK: rev w1, w2 - 0x41 0x0c 0xc0 0xda -# CHECK: rev x1, x2 - 0x41 0x04 0xc0 0x5a -# CHECK: rev16 w1, w2 - 0x41 0x04 0xc0 0xda -# CHECK: rev16 x1, x2 - 0x41 0x08 0xc0 0xda -# CHECK: rev32 x1, x2 - -#==---------------------------------------------------------------------------== -# 6.6.1 Multiply-add instructions -#==---------------------------------------------------------------------------== - -0x41 0x10 0x03 0x1b -0x41 0x10 0x03 0x9b -0x41 0x90 0x03 0x1b -0x41 0x90 0x03 0x9b -0x41 0x10 0x23 0x9b -0x41 0x90 0x23 0x9b -0x41 0x10 0xa3 0x9b -0x41 0x90 0xa3 0x9b - -# CHECK: madd w1, w2, w3, w4 -# CHECK: madd x1, x2, x3, x4 -# CHECK: msub w1, w2, w3, w4 -# CHECK: msub x1, x2, x3, x4 -# CHECK: smaddl x1, w2, w3, x4 -# CHECK: smsubl x1, w2, w3, x4 -# CHECK: umaddl x1, w2, w3, x4 -# CHECK: umsubl x1, w2, w3, x4 - -#==---------------------------------------------------------------------------== -# Multiply-high instructions -#==---------------------------------------------------------------------------== - -0x41 0x7c 0x43 0x9b -0x41 0x7c 0xc3 0x9b - -# CHECK: smulh x1, x2, x3 -# CHECK: umulh x1, x2, x3 - -#==---------------------------------------------------------------------------== -# Move immediate instructions -#==---------------------------------------------------------------------------== - -0x20 0x00 0x80 0x52 -0x20 0x00 0x80 0xd2 -0x20 0x00 0xa0 0x52 -0x20 0x00 0xa0 0xd2 - -# CHECK: movz w0, #0x1 -# CHECK: movz x0, #0x1 -# CHECK: movz w0, #0x1, lsl #16 -# CHECK: movz x0, #0x1, lsl #16 - -0x40 0x00 0x80 0x12 -0x40 0x00 0x80 0x92 -0x40 0x00 0xa0 0x12 -0x40 0x00 0xa0 0x92 - -# CHECK: movn w0, #0x2 -# CHECK: movn x0, #0x2 -# CHECK: movn w0, #0x2, lsl #16 -# CHECK: movn x0, #0x2, lsl #16 - -0x20 0x00 0x80 0x72 -0x20 0x00 0x80 0xf2 -0x20 0x00 0xa0 0x72 -0x20 0x00 0xa0 0xf2 - -# CHECK: movk w0, #0x1 -# CHECK: movk x0, #0x1 -# CHECK: movk w0, #0x1, lsl #16 -# CHECK: movk x0, #0x1, lsl #16 - -#==---------------------------------------------------------------------------== -# Conditionally set flags instructions -#==---------------------------------------------------------------------------== - - 0x1f 0x00 0x00 0x31 -# CHECK: cmn w0, #0 - 0x1f 0xfc 0x03 0xb1 -# CHECK: x0, #255 - - 0x23 0x08 0x42 0x3a -# CHECK: ccmn w1, #2, #3, eq - 0x23 0x08 0x42 0xba -# CHECK: ccmn x1, #2, #3, eq - 0x23 0x08 0x42 0x7a -# CHECK: ccmp w1, #2, #3, eq - 0x23 0x08 0x42 0xfa -# CHECK: ccmp x1, #2, #3, eq - - 0x23 0x00 0x42 0x3a -# CHECK: ccmn w1, w2, #3, eq - 0x23 0x00 0x42 0xba -# CHECK: ccmn x1, x2, #3, eq - 0x23 0x00 0x42 0x7a -# CHECK: ccmp w1, w2, #3, eq - 0x23 0x00 0x42 0xfa -# CHECK: ccmp x1, x2, #3, eq - -#==---------------------------------------------------------------------------== -# Conditional select instructions -#==---------------------------------------------------------------------------== - - 0x41 0x00 0x83 0x1a -# CHECK: csel w1, w2, w3, eq - 0x41 0x00 0x83 0x9a -# CHECK: csel x1, x2, x3, eq - 0x41 0x04 0x83 0x1a -# CHECK: csinc w1, w2, w3, eq - 0x41 0x04 0x83 0x9a -# CHECK: csinc x1, x2, x3, eq - 0x41 0x00 0x83 0x5a -# CHECK: csinv w1, w2, w3, eq - 0x41 0x00 0x83 0xda -# CHECK: csinv x1, x2, x3, eq - 0x41 0x04 0x83 0x5a -# CHECK: csneg w1, w2, w3, eq - 0x41 0x04 0x83 0xda -# CHECK: csneg x1, x2, x3, eq diff --git a/llvm/test/MC/Disassembler/ARM64/basic-a64-undefined.txt b/llvm/test/MC/Disassembler/ARM64/basic-a64-undefined.txt deleted file mode 100644 index 0e15af63e68..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/basic-a64-undefined.txt +++ /dev/null @@ -1,31 +0,0 @@ -# These spawn another process so they're rather expensive. Not many. - -# LDR/STR: undefined if option field is 10x or 00x. -# RUN: echo "0x00 0x08 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x88 0x20 0xf8" | llvm-mc -triple arm64 -disassemble 2>&1 | FileCheck %s - -# Instructions notionally in the add/sub (extended register) sheet, but with -# invalid shift amount or "opt" field. -# RUN: echo "0x00 0x10 0xa0 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x10 0x60 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x14 0x20 0x0b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s - -# MOVK with sf == 0 and hw<1> == 1 is unallocated. -# RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s - -# ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'. -# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s - -# UBFM is undefined when s == 0 and imms<5> or immr<5> is 1. -# RUN: echo "0x00 0x80 0x00 0x53" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s - -# EXT on vectors of i8 must have imm<3> = 0. -# RUN: echo "0x00 0x40 0x00 0x2e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s - -# SCVTF on fixed point W-registers is undefined if scale<5> == 0. -# Same with FCVTZS and FCVTZU. -# RUN: echo "0x00 0x00 0x02 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s -# RUN: echo "0x00 0x00 0x18 0x1e" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s - -# CHECK: invalid instruction encoding diff --git a/llvm/test/MC/Disassembler/ARM64/bitfield.txt b/llvm/test/MC/Disassembler/ARM64/bitfield.txt deleted file mode 100644 index d620cb3b217..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/bitfield.txt +++ /dev/null @@ -1,29 +0,0 @@ -# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s - -#==---------------------------------------------------------------------------== -# 5.4.4 Bitfield Operations -#==---------------------------------------------------------------------------== - -0x41 0x3c 0x01 0x33 -0x41 0x3c 0x41 0xb3 -0x41 0x3c 0x01 0x13 -0x41 0x3c 0x41 0x93 -0x41 0x3c 0x01 0x53 -0x41 0x3c 0x41 0xd3 - -# CHECK: bfxil w1, w2, #1, #15 -# CHECK: bfxil x1, x2, #1, #15 -# CHECK: sbfx w1, w2, #1, #15 -# CHECK: sbfx x1, x2, #1, #15 -# CHECK: ubfx w1, w2, #1, #15 -# CHECK: ubfx x1, x2, #1, #15 - -#==---------------------------------------------------------------------------== -# 5.4.5 Extract (immediate) -#==---------------------------------------------------------------------------== - -0x41 0x3c 0x83 0x13 -0x62 0x04 0xc4 0x93 - -# CHECK: extr w1, w2, w3, #15 -# CHECK: extr x2, x3, x4, #1 diff --git a/llvm/test/MC/Disassembler/ARM64/branch.txt b/llvm/test/MC/Disassembler/ARM64/branch.txt deleted file mode 100644 index 6af1ad886a4..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/branch.txt +++ /dev/null @@ -1,75 +0,0 @@ -# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s - -#----------------------------------------------------------------------------- -# Unconditional branch (register) instructions. -#----------------------------------------------------------------------------- - - 0xc0 0x03 0x5f 0xd6 -# CHECK: ret - 0x20 0x00 0x5f 0xd6 -# CHECK: ret x1 - 0xe0 0x03 0xbf 0xd6 -# CHECK: drps - 0xe0 0x03 0x9f 0xd6 -# CHECK: eret - 0xa0 0x00 0x1f 0xd6 -# CHECK: br x5 - 0x20 0x01 0x3f 0xd6 -# CHECK: blr x9 - 0x0B 0x00 0x18 0x37 -# CHECK: tbnz w11, #3, #0 - -#----------------------------------------------------------------------------- -# Exception generation instructions. -#----------------------------------------------------------------------------- - - 0x20 0x00 0x20 0xd4 -# CHECK: brk #0x1 - 0x41 0x00 0xa0 0xd4 -# CHECK: dcps1 #0x2 - 0x62 0x00 0xa0 0xd4 -# CHECK: dcps2 #0x3 - 0x83 0x00 0xa0 0xd4 -# CHECK: dcps3 #0x4 - 0xa0 0x00 0x40 0xd4 -# CHECK: hlt #0x5 - 0xc2 0x00 0x00 0xd4 -# CHECK: hvc #0x6 - 0xe3 0x00 0x00 0xd4 -# CHECK: smc #0x7 - 0x01 0x01 0x00 0xd4 -# CHECK: svc #0x8 - -#----------------------------------------------------------------------------- -# PC-relative branches (both positive and negative displacement) -#----------------------------------------------------------------------------- - - 0x07 0x00 0x00 0x14 -# CHECK: b #28 - 0x06 0x00 0x00 0x94 -# CHECK: bl #24 - 0xa1 0x00 0x00 0x54 -# CHECK: b.ne #20 - 0x80 0x00 0x08 0x36 -# CHECK: tbz w0, #1, #16 - 0xe1 0xff 0xf7 0x36 -# CHECK: tbz w1, #30, #-4 - 0x60 0x00 0x08 0x37 -# CHECK: tbnz w0, #1, #12 - 0x40 0x00 0x00 0xb4 -# CHECK: cbz x0, #8 - 0x20 0x00 0x00 0xb5 -# CHECK: cbnz x0, #4 - 0x1f 0x20 0x03 0xd5 -# CHECK: nop - 0xff 0xff 0xff 0x17 -# CHECK: b #-4 - 0xc1 0xff 0xff 0x54 -# CHECK: b.ne #-8 - 0xa0 0xff 0x0f 0x36 -# CHECK: tbz w0, #1, #-12 - 0x80 0xff 0xff 0xb4 -# CHECK: cbz x0, #-16 - 0x1f 0x20 0x03 0xd5 -# CHECK: nop - diff --git a/llvm/test/MC/Disassembler/ARM64/canonical-form.txt b/llvm/test/MC/Disassembler/ARM64/canonical-form.txt deleted file mode 100644 index 1c94b13b4ac..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/canonical-form.txt +++ /dev/null @@ -1,21 +0,0 @@ -# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble < %s | FileCheck %s - -0x00 0x08 0x00 0xc8 - -# CHECK: stxr w0, x0, [x0] - -0x00 0x00 0x40 0x9b - -# CHECK: smulh x0, x0, x0 - -0x08 0x20 0x21 0x1e - -# CHECK: fcmp s0, #0.0 - -0x1f 0x00 0x00 0x11 - -# CHECK: mov wsp, w0 - -0x00 0x7c 0x00 0x13 - -# CHECK: asr w0, w0, #0 diff --git a/llvm/test/MC/Disassembler/ARM64/crc32.txt b/llvm/test/MC/Disassembler/ARM64/crc32.txt deleted file mode 100644 index 51717ee2862..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/crc32.txt +++ /dev/null @@ -1,18 +0,0 @@ -# RUN: llvm-mc -triple=arm64 -mattr=+crc -disassemble < %s | FileCheck %s - -# CHECK: crc32b w5, w7, w20 -# CHECK: crc32h w28, wzr, w30 -# CHECK: crc32w w0, w1, w2 -# CHECK: crc32x w7, w9, x20 -# CHECK: crc32cb w9, w5, w4 -# CHECK: crc32ch w13, w17, w25 -# CHECK: crc32cw wzr, w3, w5 -# CHECK: crc32cx w18, w16, xzr -0xe5 0x40 0xd4 0x1a -0xfc 0x47 0xde 0x1a -0x20 0x48 0xc2 0x1a -0x27 0x4d 0xd4 0x9a -0xa9 0x50 0xc4 0x1a -0x2d 0x56 0xd9 0x1a -0x7f 0x58 0xc5 0x1a -0x12 0x5e 0xdf 0x9a diff --git a/llvm/test/MC/Disassembler/ARM64/crypto.txt b/llvm/test/MC/Disassembler/ARM64/crypto.txt deleted file mode 100644 index b905b92c636..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/crypto.txt +++ /dev/null @@ -1,47 +0,0 @@ -# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto --disassemble < %s | FileCheck %s -# RUN: llvm-mc -triple arm64-apple-darwin -mattr=crypto -output-asm-variant=1 --disassemble < %s | FileCheck %s --check-prefix=CHECK-APPLE - - 0x20 0x48 0x28 0x4e - 0x20 0x58 0x28 0x4e - 0x20 0x68 0x28 0x4e - 0x20 0x78 0x28 0x4e - 0x20 0x00 0x02 0x5e - 0x20 0x10 0x02 0x5e - 0x20 0x20 0x02 0x5e - 0x20 0x30 0x02 0x5e - 0x20 0x40 0x02 0x5e - 0x20 0x50 0x02 0x5e - 0x20 0x60 0x02 0x5e - 0x20 0x08 0x28 0x5e - 0x20 0x18 0x28 0x5e - 0x20 0x28 0x28 0x5e - -# CHECK: aese v0.16b, v1.16b -# CHECK: aesd v0.16b, v1.16b -# CHECK: aesmc v0.16b, v1.16b -# CHECK: aesimc v0.16b, v1.16b -# CHECK: sha1c q0, s1, v2.4s -# CHECK: sha1p q0, s1, v2.4s -# CHECK: sha1m q0, s1, v2.4s -# CHECK: sha1su0 v0.4s, v1.4s, v2 -# CHECK: sha256h q0, q1, v2.4s -# CHECK: sha256h2 q0, q1, v2.4s -# CHECK: sha256su1 v0.4s, v1.4s, v2.4s -# CHECK: sha1h s0, s1 -# CHECK: sha1su1 v0.4s, v1.4s -# CHECK: sha256su0 v0.4s, v1.4s - -# CHECK-APPLE: aese.16b v0, v1 -# CHECK-APPLE: aesd.16b v0, v1 -# CHECK-APPLE: aesmc.16b v0, v1 -# CHECK-APPLE: aesimc.16b v0, v1 -# CHECK-APPLE: sha1c.4s q0, s1, v2 -# CHECK-APPLE: sha1p.4s q0, s1, v2 -# CHECK-APPLE: sha1m.4s q0, s1, v2 -# CHECK-APPLE: sha1su0.4s v0, v1, v2 -# CHECK-APPLE: sha256h.4s q0, q1, v2 -# CHECK-APPLE: sha256h2.4s q0, q1, v2 -# CHECK-APPLE: sha256su1.4s v0, v1, v2 -# CHECK-APPLE: sha1h s0, s1 -# CHECK-APPLE: sha1su1.4s v0, v1 -# CHECK-APPLE: sha256su0.4s v0, v1 diff --git a/llvm/test/MC/Disassembler/ARM64/invalid-logical.txt b/llvm/test/MC/Disassembler/ARM64/invalid-logical.txt deleted file mode 100644 index 8a4ecb664ed..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/invalid-logical.txt +++ /dev/null @@ -1,6 +0,0 @@ -# RUN: llvm-mc -triple arm64-apple-darwin -disassemble < %s 2>&1 | FileCheck %s - -# rdar://15226511 -0x7b 0xbf 0x25 0x72 -# CHECK: invalid instruction encoding -# CHECK-NEXT: 0x7b 0xbf 0x25 0x72 diff --git a/llvm/test/MC/Disassembler/ARM64/lit.local.cfg b/llvm/test/MC/Disassembler/ARM64/lit.local.cfg deleted file mode 100644 index 46a946845e1..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/lit.local.cfg +++ /dev/null @@ -1,5 +0,0 @@ -config.suffixes = ['.txt'] - -targets = set(config.root.targets_to_build.split()) -if not 'ARM64' in targets: - config.unsupported = True diff --git a/llvm/test/MC/Disassembler/ARM64/logical.txt b/llvm/test/MC/Disassembler/ARM64/logical.txt deleted file mode 100644 index e3cb3ebe7e0..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/logical.txt +++ /dev/null @@ -1,223 +0,0 @@ -# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s - -#==---------------------------------------------------------------------------== -# 5.4.2 Logical (immediate) -#==---------------------------------------------------------------------------== - -0x00 0x00 0x00 0x12 -0x00 0x00 0x40 0x92 -0x41 0x0c 0x00 0x12 -0x41 0x0c 0x40 0x92 -0xbf 0xec 0x7c 0x92 -0x00 0x00 0x00 0x72 -0x00 0x00 0x40 0xf2 -0x41 0x0c 0x00 0x72 -0x41 0x0c 0x40 0xf2 -0x5f 0x0c 0x40 0xf2 - -# CHECK: and w0, w0, #0x1 -# CHECK: and x0, x0, #0x1 -# CHECK: and w1, w2, #0xf -# CHECK: and x1, x2, #0xf -# CHECK: and sp, x5, #0xfffffffffffffff0 -# CHECK: ands w0, w0, #0x1 -# CHECK: ands x0, x0, #0x1 -# CHECK: ands w1, w2, #0xf -# CHECK: ands x1, x2, #0xf -# CHECK: tst x2, #0xf - -0x41 0x00 0x12 0x52 -0x41 0x00 0x71 0xd2 -0x5f 0x00 0x71 0xd2 - -# CHECK: eor w1, w2, #0x4000 -# CHECK: eor x1, x2, #0x8000 -# CHECK: eor sp, x2, #0x8000 - -0x41 0x00 0x12 0x32 -0x41 0x00 0x71 0xb2 -0x5f 0x00 0x71 0xb2 - -# CHECK: orr w1, w2, #0x4000 -# CHECK: orr x1, x2, #0x8000 -# CHECK: orr sp, x2, #0x8000 - -#==---------------------------------------------------------------------------== -# 5.5.3 Logical (shifted register) -#==---------------------------------------------------------------------------== - -0x41 0x00 0x03 0x0a -0x41 0x00 0x03 0x8a -0x41 0x08 0x03 0x0a -0x41 0x08 0x03 0x8a -0x41 0x08 0x43 0x0a -0x41 0x08 0x43 0x8a -0x41 0x08 0x83 0x0a -0x41 0x08 0x83 0x8a -0x41 0x08 0xc3 0x0a -0x41 0x08 0xc3 0x8a - -# CHECK: and w1, w2, w3 -# CHECK: and x1, x2, x3 -# CHECK: and w1, w2, w3, lsl #2 -# CHECK: and x1, x2, x3, lsl #2 -# CHECK: and w1, w2, w3, lsr #2 -# CHECK: and x1, x2, x3, lsr #2 -# CHECK: and w1, w2, w3, asr #2 -# CHECK: and x1, x2, x3, asr #2 -# CHECK: and w1, w2, w3, ror #2 -# CHECK: and x1, x2, x3, ror #2 - -0x41 0x00 0x03 0x6a -0x41 0x00 0x03 0xea -0x41 0x08 0x03 0x6a -0x41 0x08 0x03 0xea -0x41 0x08 0x43 0x6a -0x41 0x08 0x43 0xea -0x41 0x08 0x83 0x6a -0x41 0x08 0x83 0xea -0x41 0x08 0xc3 0x6a -0x41 0x08 0xc3 0xea - -# CHECK: ands w1, w2, w3 -# CHECK: ands x1, x2, x3 -# CHECK: ands w1, w2, w3, lsl #2 -# CHECK: ands x1, x2, x3, lsl #2 -# CHECK: ands w1, w2, w3, lsr #2 -# CHECK: ands x1, x2, x3, lsr #2 -# CHECK: ands w1, w2, w3, asr #2 -# CHECK: ands x1, x2, x3, asr #2 -# CHECK: ands w1, w2, w3, ror #2 -# CHECK: ands x1, x2, x3, ror #2 - -0x41 0x00 0x23 0x0a -0x41 0x00 0x23 0x8a -0x41 0x0c 0x23 0x0a -0x41 0x0c 0x23 0x8a -0x41 0x0c 0x63 0x0a -0x41 0x0c 0x63 0x8a -0x41 0x0c 0xa3 0x0a -0x41 0x0c 0xa3 0x8a -0x41 0x0c 0xe3 0x0a -0x41 0x0c 0xe3 0x8a - -# CHECK: bic w1, w2, w3 -# CHECK: bic x1, x2, x3 -# CHECK: bic w1, w2, w3, lsl #3 -# CHECK: bic x1, x2, x3, lsl #3 -# CHECK: bic w1, w2, w3, lsr #3 -# CHECK: bic x1, x2, x3, lsr #3 -# CHECK: bic w1, w2, w3, asr #3 -# CHECK: bic x1, x2, x3, asr #3 -# CHECK: bic w1, w2, w3, ror #3 -# CHECK: bic x1, x2, x3, ror #3 - -0x41 0x00 0x23 0x6a -0x41 0x00 0x23 0xea -0x41 0x0c 0x23 0x6a -0x41 0x0c 0x23 0xea -0x41 0x0c 0x63 0x6a -0x41 0x0c 0x63 0xea -0x41 0x0c 0xa3 0x6a -0x41 0x0c 0xa3 0xea -0x41 0x0c 0xe3 0x6a -0x41 0x0c 0xe3 0xea - -# CHECK: bics w1, w2, w3 -# CHECK: bics x1, x2, x3 -# CHECK: bics w1, w2, w3, lsl #3 -# CHECK: bics x1, x2, x3, lsl #3 -# CHECK: bics w1, w2, w3, lsr #3 -# CHECK: bics x1, x2, x3, lsr #3 -# CHECK: bics w1, w2, w3, asr #3 -# CHECK: bics x1, x2, x3, asr #3 -# CHECK: bics w1, w2, w3, ror #3 -# CHECK: bics x1, x2, x3, ror #3 - -0x41 0x00 0x23 0x4a -0x41 0x00 0x23 0xca -0x41 0x10 0x23 0x4a -0x41 0x10 0x23 0xca -0x41 0x10 0x63 0x4a -0x41 0x10 0x63 0xca -0x41 0x10 0xa3 0x4a -0x41 0x10 0xa3 0xca -0x41 0x10 0xe3 0x4a -0x41 0x10 0xe3 0xca - -# CHECK: eon w1, w2, w3 -# CHECK: eon x1, x2, x3 -# CHECK: eon w1, w2, w3, lsl #4 -# CHECK: eon x1, x2, x3, lsl #4 -# CHECK: eon w1, w2, w3, lsr #4 -# CHECK: eon x1, x2, x3, lsr #4 -# CHECK: eon w1, w2, w3, asr #4 -# CHECK: eon x1, x2, x3, asr #4 -# CHECK: eon w1, w2, w3, ror #4 -# CHECK: eon x1, x2, x3, ror #4 - -0x41 0x00 0x03 0x4a -0x41 0x00 0x03 0xca -0x41 0x14 0x03 0x4a -0x41 0x14 0x03 0xca -0x41 0x14 0x43 0x4a -0x41 0x14 0x43 0xca -0x41 0x14 0x83 0x4a -0x41 0x14 0x83 0xca -0x41 0x14 0xc3 0x4a -0x41 0x14 0xc3 0xca - -# CHECK: eor w1, w2, w3 -# CHECK: eor x1, x2, x3 -# CHECK: eor w1, w2, w3, lsl #5 -# CHECK: eor x1, x2, x3, lsl #5 -# CHECK: eor w1, w2, w3, lsr #5 -# CHECK: eor x1, x2, x3, lsr #5 -# CHECK: eor w1, w2, w3, asr #5 -# CHECK: eor x1, x2, x3, asr #5 -# CHECK: eor w1, w2, w3, ror #5 -# CHECK: eor x1, x2, x3, ror #5 - -0x41 0x00 0x03 0x2a -0x41 0x00 0x03 0xaa -0x41 0x18 0x03 0x2a -0x41 0x18 0x03 0xaa -0x41 0x18 0x43 0x2a -0x41 0x18 0x43 0xaa -0x41 0x18 0x83 0x2a -0x41 0x18 0x83 0xaa -0x41 0x18 0xc3 0x2a -0x41 0x18 0xc3 0xaa - -# CHECK: orr w1, w2, w3 -# CHECK: orr x1, x2, x3 -# CHECK: orr w1, w2, w3, lsl #6 -# CHECK: orr x1, x2, x3, lsl #6 -# CHECK: orr w1, w2, w3, lsr #6 -# CHECK: orr x1, x2, x3, lsr #6 -# CHECK: orr w1, w2, w3, asr #6 -# CHECK: orr x1, x2, x3, asr #6 -# CHECK: orr w1, w2, w3, ror #6 -# CHECK: orr x1, x2, x3, ror #6 - -0x41 0x00 0x23 0x2a -0x41 0x00 0x23 0xaa -0x41 0x1c 0x23 0x2a -0x41 0x1c 0x23 0xaa -0x41 0x1c 0x63 0x2a -0x41 0x1c 0x63 0xaa -0x41 0x1c 0xa3 0x2a -0x41 0x1c 0xa3 0xaa -0x41 0x1c 0xe3 0x2a -0x41 0x1c 0xe3 0xaa - -# CHECK: orn w1, w2, w3 -# CHECK: orn x1, x2, x3 -# CHECK: orn w1, w2, w3, lsl #7 -# CHECK: orn x1, x2, x3, lsl #7 -# CHECK: orn w1, w2, w3, lsr #7 -# CHECK: orn x1, x2, x3, lsr #7 -# CHECK: orn w1, w2, w3, asr #7 -# CHECK: orn x1, x2, x3, asr #7 -# CHECK: orn w1, w2, w3, ror #7 -# CHECK: orn x1, x2, x3, ror #7 diff --git a/llvm/test/MC/Disassembler/ARM64/memory.txt b/llvm/test/MC/Disassembler/ARM64/memory.txt deleted file mode 100644 index 54556a10b8a..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/memory.txt +++ /dev/null @@ -1,564 +0,0 @@ -# RUN: llvm-mc --disassemble -triple arm64-apple-darwin < %s | FileCheck %s - -#----------------------------------------------------------------------------- -# Indexed loads -#----------------------------------------------------------------------------- - - 0x85 0x14 0x40 0xb9 - 0x64 0x00 0x40 0xf9 - 0xe2 0x13 0x40 0xf9 - 0xe5 0x07 0x40 0x3d - 0xe6 0x07 0x40 0x7d - 0xe7 0x07 0x40 0xbd - 0xe8 0x07 0x40 0xfd - 0xe9 0x07 0xc0 0x3d - 0x64 0x00 0x40 0x39 - 0x20 0x78 0xa0 0xb8 - 0x85 0x50 0x40 0x39 - -# CHECK: ldr w5, [x4, #20] -# CHECK: ldr x4, [x3] -# CHECK: ldr x2, [sp, #32] -# CHECK: ldr b5, [sp, #1] -# CHECK: ldr h6, [sp, #2] -# CHECK: ldr s7, [sp, #4] -# CHECK: ldr d8, [sp, #8] -# CHECK: ldr q9, [sp, #16] -# CHECK: ldrb w4, [x3] -# CHECK: ldrsw x0, [x1, x0, lsl #2] -# CHECK: ldrb w5, [x4, #20] -# CHECK: ldrsb w9, [x3] -# CHECK: ldrsb x2, [sp, #128] -# CHECK: ldrh w2, [sp, #32] -# CHECK: ldrsh w3, [sp, #32] -# CHECK: ldrsh x5, [x9, #24] -# CHECK: ldrsw x9, [sp, #512] -# CHECK: prfm pldl3strm, [sp, #32] - - 0x69 0x00 0xc0 0x39 - 0xe2 0x03 0x82 0x39 - 0xe2 0x43 0x40 0x79 - 0xe3 0x43 0xc0 0x79 - 0x25 0x31 0x80 0x79 - 0xe9 0x03 0x82 0xb9 - 0xe5 0x13 0x80 0xf9 - 0x40 0x00 0x80 0xf9 - 0x41 0x00 0x80 0xf9 - 0x42 0x00 0x80 0xf9 - 0x43 0x00 0x80 0xf9 - 0x44 0x00 0x80 0xf9 - 0x45 0x00 0x80 0xf9 - 0x50 0x00 0x80 0xf9 - 0x51 0x00 0x80 0xf9 - 0x52 0x00 0x80 0xf9 - 0x53 0x00 0x80 0xf9 - 0x54 0x00 0x80 0xf9 - 0x55 0x00 0x80 0xf9 - -# CHECK: prfm pldl1keep, [x2] -# CHECK: prfm pldl1strm, [x2] -# CHECK: prfm pldl2keep, [x2] -# CHECK: prfm pldl2strm, [x2] -# CHECK: prfm pldl3keep, [x2] -# CHECK: prfm pldl3strm, [x2] -# CHECK: prfm pstl1keep, [x2] -# CHECK: prfm pstl1strm, [x2] -# CHECK: prfm pstl2keep, [x2] -# CHECK: prfm pstl2strm, [x2] -# CHECK: prfm pstl3keep, [x2] -# CHECK: prfm pstl3strm, [x2] - -#----------------------------------------------------------------------------- -# Indexed stores -#----------------------------------------------------------------------------- - - 0x64 0x00 0x00 0xf9 - 0xe2 0x13 0x00 0xf9 - 0x85 0x14 0x00 0xb9 - 0xe5 0x07 0x00 0x3d - 0xe6 0x07 0x00 0x7d - 0xe7 0x07 0x00 0xbd - 0xe8 0x07 0x00 0xfd - 0xe9 0x07 0x80 0x3d - 0x64 0x00 0x00 0x39 - 0x85 0x50 0x00 0x39 - 0xe2 0x43 0x00 0x79 - 0x00 0xe8 0x20 0x38 - 0x00 0x48 0x20 0x38 - -# CHECK: str x4, [x3] -# CHECK: str x2, [sp, #32] -# CHECK: str w5, [x4, #20] -# CHECK: str b5, [sp, #1] -# CHECK: str h6, [sp, #2] -# CHECK: str s7, [sp, #4] -# CHECK: str d8, [sp, #8] -# CHECK: str q9, [sp, #16] -# CHECK: strb w4, [x3] -# CHECK: strb w5, [x4, #20] -# CHECK: strh w2, [sp, #32] -# CHECK: strb w0, [x0, x0, sxtx] -# CHECK: strb w0, [x0, w0, uxtw] - -#----------------------------------------------------------------------------- -# Unscaled immediate loads and stores -#----------------------------------------------------------------------------- - - 0x62 0x00 0x40 0xb8 - 0xe2 0x83 0x41 0xb8 - 0x62 0x00 0x40 0xf8 - 0xe2 0x83 0x41 0xf8 - 0xe5 0x13 0x40 0x3c - 0xe6 0x23 0x40 0x7c - 0xe7 0x43 0x40 0xbc - 0xe8 0x83 0x40 0xfc - 0xe9 0x03 0xc1 0x3c - 0x69 0x00 0xc0 0x38 - 0xe2 0x03 0x88 0x38 - 0xe3 0x03 0xc2 0x78 - 0x25 0x81 0x81 0x78 - 0xe9 0x03 0x98 0xb8 - -# CHECK: ldur w2, [x3] -# CHECK: ldur w2, [sp, #24] -# CHECK: ldur x2, [x3] -# CHECK: ldur x2, [sp, #24] -# CHECK: ldur b5, [sp, #1] -# CHECK: ldur h6, [sp, #2] -# CHECK: ldur s7, [sp, #4] -# CHECK: ldur d8, [sp, #8] -# CHECK: ldur q9, [sp, #16] -# CHECK: ldursb w9, [x3] -# CHECK: ldursb x2, [sp, #128] -# CHECK: ldursh w3, [sp, #32] -# CHECK: ldursh x5, [x9, #24] -# CHECK: ldursw x9, [sp, #-128] - - 0x64 0x00 0x00 0xb8 - 0xe2 0x03 0x02 0xb8 - 0x64 0x00 0x00 0xf8 - 0xe2 0x03 0x02 0xf8 - 0x85 0x40 0x01 0xb8 - 0xe5 0x13 0x00 0x3c - 0xe6 0x23 0x00 0x7c - 0xe7 0x43 0x00 0xbc - 0xe8 0x83 0x00 0xfc - 0xe9 0x03 0x81 0x3c - 0x64 0x00 0x00 0x38 - 0x85 0x40 0x01 0x38 - 0xe2 0x03 0x02 0x78 - 0xe5 0x03 0x82 0xf8 - -# CHECK: stur w4, [x3] -# CHECK: stur w2, [sp, #32] -# CHECK: stur x4, [x3] -# CHECK: stur x2, [sp, #32] -# CHECK: stur w5, [x4, #20] -# CHECK: stur b5, [sp, #1] -# CHECK: stur h6, [sp, #2] -# CHECK: stur s7, [sp, #4] -# CHECK: stur d8, [sp, #8] -# CHECK: stur q9, [sp, #16] -# CHECK: sturb w4, [x3] -# CHECK: sturb w5, [x4, #20] -# CHECK: sturh w2, [sp, #32] -# CHECK: prfum pldl3strm, [sp, #32] - -#----------------------------------------------------------------------------- -# Unprivileged loads and stores -#----------------------------------------------------------------------------- - - 0x83 0x08 0x41 0xb8 - 0x83 0x08 0x41 0xf8 - 0x83 0x08 0x41 0x38 - 0x69 0x08 0xc0 0x38 - 0xe2 0x0b 0x88 0x38 - 0x83 0x08 0x41 0x78 - 0xe3 0x0b 0xc2 0x78 - 0x25 0x89 0x81 0x78 - 0xe9 0x0b 0x98 0xb8 - -# CHECK: ldtr w3, [x4, #16] -# CHECK: ldtr x3, [x4, #16] -# CHECK: ldtrb w3, [x4, #16] -# CHECK: ldtrsb w9, [x3] -# CHECK: ldtrsb x2, [sp, #128] -# CHECK: ldtrh w3, [x4, #16] -# CHECK: ldtrsh w3, [sp, #32] -# CHECK: ldtrsh x5, [x9, #24] -# CHECK: ldtrsw x9, [sp, #-128] - - 0x85 0x48 0x01 0xb8 - 0x64 0x08 0x00 0xf8 - 0xe2 0x0b 0x02 0xf8 - 0x64 0x08 0x00 0x38 - 0x85 0x48 0x01 0x38 - 0xe2 0x0b 0x02 0x78 - -# CHECK: sttr w5, [x4, #20] -# CHECK: sttr x4, [x3] -# CHECK: sttr x2, [sp, #32] -# CHECK: sttrb w4, [x3] -# CHECK: sttrb w5, [x4, #20] -# CHECK: sttrh w2, [sp, #32] - -#----------------------------------------------------------------------------- -# Pre-indexed loads and stores -#----------------------------------------------------------------------------- - - 0xfd 0x8c 0x40 0xf8 - 0xfe 0x8c 0x40 0xf8 - 0x05 0x1c 0x40 0x3c - 0x06 0x2c 0x40 0x7c - 0x07 0x4c 0x40 0xbc - 0x08 0x8c 0x40 0xfc - 0x09 0x0c 0xc1 0x3c - -# CHECK: ldr x29, [x7, #8]! -# CHECK: ldr x30, [x7, #8]! -# CHECK: ldr b5, [x0, #1]! -# CHECK: ldr h6, [x0, #2]! -# CHECK: ldr s7, [x0, #4]! -# CHECK: ldr d8, [x0, #8]! -# CHECK: ldr q9, [x0, #16]! - - 0xfe 0x8c 0x1f 0xf8 - 0xfd 0x8c 0x1f 0xf8 - 0x05 0xfc 0x1f 0x3c - 0x06 0xec 0x1f 0x7c - 0x07 0xcc 0x1f 0xbc - 0x08 0x8c 0x1f 0xfc - 0x09 0x0c 0x9f 0x3c - -# CHECK: str x30, [x7, #-8]! -# CHECK: str x29, [x7, #-8]! -# CHECK: str b5, [x0, #-1]! -# CHECK: str h6, [x0, #-2]! -# CHECK: str s7, [x0, #-4]! -# CHECK: str d8, [x0, #-8]! -# CHECK: str q9, [x0, #-16]! - -#----------------------------------------------------------------------------- -# post-indexed loads and stores -#----------------------------------------------------------------------------- - - 0xfe 0x84 0x1f 0xf8 - 0xfd 0x84 0x1f 0xf8 - 0x05 0xf4 0x1f 0x3c - 0x06 0xe4 0x1f 0x7c - 0x07 0xc4 0x1f 0xbc - 0x08 0x84 0x1f 0xfc - 0x09 0x04 0x9f 0x3c - -# CHECK: str x30, [x7], #-8 -# CHECK: str x29, [x7], #-8 -# CHECK: str b5, [x0], #-1 -# CHECK: str h6, [x0], #-2 -# CHECK: str s7, [x0], #-4 -# CHECK: str d8, [x0], #-8 -# CHECK: str q9, [x0], #-16 - - 0xfd 0x84 0x40 0xf8 - 0xfe 0x84 0x40 0xf8 - 0x05 0x14 0x40 0x3c - 0x06 0x24 0x40 0x7c - 0x07 0x44 0x40 0xbc - 0x08 0x84 0x40 0xfc - 0x09 0x04 0xc1 0x3c - -# CHECK: ldr x29, [x7], #8 -# CHECK: ldr x30, [x7], #8 -# CHECK: ldr b5, [x0], #1 -# CHECK: ldr h6, [x0], #2 -# CHECK: ldr s7, [x0], #4 -# CHECK: ldr d8, [x0], #8 -# CHECK: ldr q9, [x0], #16 - -#----------------------------------------------------------------------------- -# Load/Store pair (indexed offset) -#----------------------------------------------------------------------------- - - 0xe3 0x09 0x42 0x29 - 0xe4 0x27 0x7f 0xa9 - 0xc2 0x0d 0x42 0x69 - 0xe2 0x0f 0x7e 0x69 - 0x4a 0x04 0x48 0x2d - 0x4a 0x04 0x40 0x6d - -# CHECK: ldp w3, w2, [x15, #16] -# CHECK: ldp x4, x9, [sp, #-16] -# CHECK: ldpsw x2, x3, [x14, #16] -# CHECK: ldpsw x2, x3, [sp, #-16] -# CHECK: ldp s10, s1, [x2, #64] -# CHECK: ldp d10, d1, [x2] - - 0xe3 0x09 0x02 0x29 - 0xe4 0x27 0x3f 0xa9 - 0x4a 0x04 0x08 0x2d - 0x4a 0x04 0x00 0x6d - -# CHECK: stp w3, w2, [x15, #16] -# CHECK: stp x4, x9, [sp, #-16] -# CHECK: stp s10, s1, [x2, #64] -# CHECK: stp d10, d1, [x2] - -#----------------------------------------------------------------------------- -# Load/Store pair (pre-indexed) -#----------------------------------------------------------------------------- - - 0xe3 0x09 0xc2 0x29 - 0xe4 0x27 0xff 0xa9 - 0xc2 0x0d 0xc2 0x69 - 0xe2 0x0f 0xfe 0x69 - 0x4a 0x04 0xc8 0x2d - 0x4a 0x04 0xc1 0x6d - -# CHECK: ldp w3, w2, [x15, #16]! -# CHECK: ldp x4, x9, [sp, #-16]! -# CHECK: ldpsw x2, x3, [x14, #16]! -# CHECK: ldpsw x2, x3, [sp, #-16]! -# CHECK: ldp s10, s1, [x2, #64]! -# CHECK: ldp d10, d1, [x2, #16]! - - 0xe3 0x09 0x82 0x29 - 0xe4 0x27 0xbf 0xa9 - 0x4a 0x04 0x88 0x2d - 0x4a 0x04 0x81 0x6d - -# CHECK: stp w3, w2, [x15, #16]! -# CHECK: stp x4, x9, [sp, #-16]! -# CHECK: stp s10, s1, [x2, #64]! -# CHECK: stp d10, d1, [x2, #16]! - -#----------------------------------------------------------------------------- -# Load/Store pair (post-indexed) -#----------------------------------------------------------------------------- - - 0xe3 0x09 0xc2 0x28 - 0xe4 0x27 0xff 0xa8 - 0xc2 0x0d 0xc2 0x68 - 0xe2 0x0f 0xfe 0x68 - 0x4a 0x04 0xc8 0x2c - 0x4a 0x04 0xc1 0x6c - -# CHECK: ldp w3, w2, [x15], #16 -# CHECK: ldp x4, x9, [sp], #-16 -# CHECK: ldpsw x2, x3, [x14], #16 -# CHECK: ldpsw x2, x3, [sp], #-16 -# CHECK: ldp s10, s1, [x2], #64 -# CHECK: ldp d10, d1, [x2], #16 - - 0xe3 0x09 0x82 0x28 - 0xe4 0x27 0xbf 0xa8 - 0x4a 0x04 0x88 0x2c - 0x4a 0x04 0x81 0x6c - -# CHECK: stp w3, w2, [x15], #16 -# CHECK: stp x4, x9, [sp], #-16 -# CHECK: stp s10, s1, [x2], #64 -# CHECK: stp d10, d1, [x2], #16 - -#----------------------------------------------------------------------------- -# Load/Store pair (no-allocate) -#----------------------------------------------------------------------------- - - 0xe3 0x09 0x42 0x28 - 0xe4 0x27 0x7f 0xa8 - 0x4a 0x04 0x48 0x2c - 0x4a 0x04 0x40 0x6c - -# CHECK: ldnp w3, w2, [x15, #16] -# CHECK: ldnp x4, x9, [sp, #-16] -# CHECK: ldnp s10, s1, [x2, #64] -# CHECK: ldnp d10, d1, [x2] - - 0xe3 0x09 0x02 0x28 - 0xe4 0x27 0x3f 0xa8 - 0x4a 0x04 0x08 0x2c - 0x4a 0x04 0x00 0x6c - -# CHECK: stnp w3, w2, [x15, #16] -# CHECK: stnp x4, x9, [sp, #-16] -# CHECK: stnp s10, s1, [x2, #64] -# CHECK: stnp d10, d1, [x2] - -#----------------------------------------------------------------------------- -# Load/Store register offset -#----------------------------------------------------------------------------- - - 0x00 0x68 0x60 0xb8 - 0x00 0x78 0x60 0xb8 - 0x00 0x68 0x60 0xf8 - 0x00 0x78 0x60 0xf8 - 0x00 0xe8 0x60 0xf8 - -# CHECK: ldr w0, [x0, x0] -# CHECK: ldr w0, [x0, x0, lsl #2] -# CHECK: ldr x0, [x0, x0] -# CHECK: ldr x0, [x0, x0, lsl #3] -# CHECK: ldr x0, [x0, x0, sxtx] - - 0x21 0x68 0x62 0x3c - 0x21 0x78 0x62 0x3c - 0x21 0x68 0x62 0x7c - 0x21 0x78 0x62 0x7c - 0x21 0x68 0x62 0xbc - 0x21 0x78 0x62 0xbc - 0x21 0x68 0x62 0xfc - 0x21 0x78 0x62 0xfc - 0x21 0x68 0xe2 0x3c - 0x21 0x78 0xe2 0x3c - -# CHECK: ldr b1, [x1, x2] -# CHECK: ldr b1, [x1, x2, lsl #0] -# CHECK: ldr h1, [x1, x2] -# CHECK: ldr h1, [x1, x2, lsl #1] -# CHECK: ldr s1, [x1, x2] -# CHECK: ldr s1, [x1, x2, lsl #2] -# CHECK: ldr d1, [x1, x2] -# CHECK: ldr d1, [x1, x2, lsl #3] -# CHECK: ldr q1, [x1, x2] -# CHECK: ldr q1, [x1, x2, lsl #4] - - 0x00 0x48 0x20 0x7c - 0xe1 0x6b 0x23 0xfc - 0xe1 0x5b 0x23 0xfc - 0xe1 0x6b 0xa3 0x3c - 0xe1 0x5b 0xa3 0x3c - -# CHECK: str h0, [x0, w0, uxtw] -# CHECK: str d1, [sp, x3] -# CHECK: str d1, [sp, w3, uxtw #3] -# CHECK: str q1, [sp, x3] -# CHECK: str q1, [sp, w3, uxtw #4] - -#----------------------------------------------------------------------------- -# Load/Store exclusive -#----------------------------------------------------------------------------- - - 0x26 0x7c 0x5f 0x08 - 0x26 0x7c 0x5f 0x48 - 0x27 0x0d 0x7f 0x88 - 0x27 0x0d 0x7f 0xc8 - -# CHECK: ldxrb w6, [x1] -# CHECK: ldxrh w6, [x1] -# CHECK: ldxp w7, w3, [x9] -# CHECK: ldxp x7, x3, [x9] - - 0x64 0x7c 0x01 0xc8 - 0x64 0x7c 0x01 0x88 - 0x64 0x7c 0x01 0x08 - 0x64 0x7c 0x01 0x48 - 0x22 0x18 0x21 0xc8 - 0x22 0x18 0x21 0x88 - -# CHECK: stxr w1, x4, [x3] -# CHECK: stxr w1, w4, [x3] -# CHECK: stxrb w1, w4, [x3] -# CHECK: stxrh w1, w4, [x3] -# CHECK: stxp w1, x2, x6, [x1] -# CHECK: stxp w1, w2, w6, [x1] - -#----------------------------------------------------------------------------- -# Load-acquire/Store-release non-exclusive -#----------------------------------------------------------------------------- - - 0xe4 0xff 0xdf 0x88 - 0xe4 0xff 0xdf 0xc8 - 0xe4 0xff 0xdf 0x08 - 0xe4 0xff 0xdf 0x48 - -# CHECK: ldar w4, [sp] -# CHECK: ldar x4, [sp] -# CHECK: ldarb w4, [sp] -# CHECK: ldarh w4, [sp] - - 0xc3 0xfc 0x9f 0x88 - 0xc3 0xfc 0x9f 0xc8 - 0xc3 0xfc 0x9f 0x08 - 0xc3 0xfc 0x9f 0x48 - -# CHECK: stlr w3, [x6] -# CHECK: stlr x3, [x6] -# CHECK: stlrb w3, [x6] -# CHECK: stlrh w3, [x6] - -#----------------------------------------------------------------------------- -# Load-acquire/Store-release exclusive -#----------------------------------------------------------------------------- - - 0x82 0xfc 0x5f 0x88 - 0x82 0xfc 0x5f 0xc8 - 0x82 0xfc 0x5f 0x08 - 0x82 0xfc 0x5f 0x48 - 0x22 0x98 0x7f 0x88 - 0x22 0x98 0x7f 0xc8 - -# CHECK: ldaxr w2, [x4] -# CHECK: ldaxr x2, [x4] -# CHECK: ldaxrb w2, [x4] -# CHECK: ldaxrh w2, [x4] -# CHECK: ldaxp w2, w6, [x1] -# CHECK: ldaxp x2, x6, [x1] - - 0x27 0xfc 0x08 0xc8 - 0x27 0xfc 0x08 0x88 - 0x27 0xfc 0x08 0x08 - 0x27 0xfc 0x08 0x48 - 0x22 0x98 0x21 0xc8 - 0x22 0x98 0x21 0x88 - -# CHECK: stlxr w8, x7, [x1] -# CHECK: stlxr w8, w7, [x1] -# CHECK: stlxrb w8, w7, [x1] -# CHECK: stlxrh w8, w7, [x1] -# CHECK: stlxp w1, x2, x6, [x1] -# CHECK: stlxp w1, w2, w6, [x1] - -#----------------------------------------------------------------------------- -# Load/Store with explicit LSL values -#----------------------------------------------------------------------------- - 0x20 0x78 0xa0 0xb8 - 0x20 0x78 0x60 0xf8 - 0x20 0x78 0x20 0xf8 - 0x20 0x78 0x60 0xb8 - 0x20 0x78 0x20 0xb8 - 0x20 0x78 0xe0 0x3c - 0x20 0x78 0xa0 0x3c - 0x20 0x78 0x60 0xfc - 0x20 0x78 0x20 0xfc - 0x20 0x78 0x60 0xbc - 0x20 0x78 0x20 0xbc - 0x20 0x78 0x60 0x7c - 0x20 0x78 0x60 0x3c - 0x20 0x78 0x60 0x38 - 0x20 0x78 0x20 0x38 - 0x20 0x78 0xe0 0x38 - 0x20 0x78 0x60 0x78 - 0x20 0x78 0x20 0x78 - 0x20 0x78 0xe0 0x78 - 0x20 0x78 0xa0 0x38 - 0x20 0x78 0xa0 0x78 - -# CHECK: ldrsw x0, [x1, x0, lsl #2] -# CHECK: ldr x0, [x1, x0, lsl #3] -# CHECK: str x0, [x1, x0, lsl #3] -# CHECK: ldr w0, [x1, x0, lsl #2] -# CHECK: str w0, [x1, x0, lsl #2] -# CHECK: ldr q0, [x1, x0, lsl #4] -# CHECK: str q0, [x1, x0, lsl #4] -# CHECK: ldr d0, [x1, x0, lsl #3] -# CHECK: str d0, [x1, x0, lsl #3] -# CHECK: ldr s0, [x1, x0, lsl #2] -# CHECK: str s0, [x1, x0, lsl #2] -# CHECK: ldr h0, [x1, x0, lsl #1] -# CHECK: ldr b0, [x1, x0, lsl #0] -# CHECK: ldrb w0, [x1, x0, lsl #0] -# CHECK: strb w0, [x1, x0, lsl #0] -# CHECK: ldrsb w0, [x1, x0, lsl #0] -# CHECK: ldrh w0, [x1, x0, lsl #1] -# CHECK: strh w0, [x1, x0, lsl #1] -# CHECK: ldrsh w0, [x1, x0, lsl #1] -# CHECK: ldrsb x0, [x1, x0, lsl #0] -# CHECK: ldrsh x0, [x1, x0, lsl #1] diff --git a/llvm/test/MC/Disassembler/ARM64/non-apple-fmov.txt b/llvm/test/MC/Disassembler/ARM64/non-apple-fmov.txt deleted file mode 100644 index 75cb95ce186..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/non-apple-fmov.txt +++ /dev/null @@ -1,7 +0,0 @@ -# RUN: llvm-mc -triple arm64 -mattr=neon -disassemble < %s | FileCheck %s - -0x00 0x00 0xae 0x9e -0x00 0x00 0xaf 0x9e - -# CHECK: fmov x0, v0.d[1] -# CHECK: fmov v0.d[1], x0 diff --git a/llvm/test/MC/Disassembler/ARM64/scalar-fp.txt b/llvm/test/MC/Disassembler/ARM64/scalar-fp.txt deleted file mode 100644 index f139700164c..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/scalar-fp.txt +++ /dev/null @@ -1,255 +0,0 @@ -# RUN: llvm-mc -triple arm64-apple-darwin -mattr=neon --disassemble -output-asm-variant=1 < %s | FileCheck %s - -#----------------------------------------------------------------------------- -# Floating-point arithmetic -#----------------------------------------------------------------------------- - -0x41 0xc0 0x20 0x1e -0x41 0xc0 0x60 0x1e - -# CHECK: fabs s1, s2 -# CHECK: fabs d1, d2 - -0x41 0x28 0x23 0x1e -0x41 0x28 0x63 0x1e - -# CHECK: fadd s1, s2, s3 -# CHECK: fadd d1, d2, d3 - -0x41 0x18 0x23 0x1e -0x41 0x18 0x63 0x1e - -# CHECK: fdiv s1, s2, s3 -# CHECK: fdiv d1, d2, d3 - -0x41 0x10 0x03 0x1f -0x41 0x10 0x43 0x1f - -# CHECK: fmadd s1, s2, s3, s4 -# CHECK: fmadd d1, d2, d3, d4 - -0x41 0x48 0x23 0x1e -0x41 0x48 0x63 0x1e -0x41 0x68 0x23 0x1e -0x41 0x68 0x63 0x1e - -# CHECK: fmax s1, s2, s3 -# CHECK: fmax d1, d2, d3 -# CHECK: fmaxnm s1, s2, s3 -# CHECK: fmaxnm d1, d2, d3 - -0x41 0x58 0x23 0x1e -0x41 0x58 0x63 0x1e -0x41 0x78 0x23 0x1e -0x41 0x78 0x63 0x1e - -# CHECK: fmin s1, s2, s3 -# CHECK: fmin d1, d2, d3 -# CHECK: fminnm s1, s2, s3 -# CHECK: fminnm d1, d2, d3 - -0x41 0x90 0x03 0x1f -0x41 0x90 0x43 0x1f - -# CHECK: fmsub s1, s2, s3, s4 -# CHECK: fmsub d1, d2, d3, d4 - -0x41 0x08 0x23 0x1e -0x41 0x08 0x63 0x1e - -# CHECK: fmul s1, s2, s3 -# CHECK: fmul d1, d2, d3 - -0x41 0x40 0x21 0x1e -0x41 0x40 0x61 0x1e - -# CHECK: fneg s1, s2 -# CHECK: fneg d1, d2 - -0x41 0x10 0x23 0x1f -0x41 0x10 0x63 0x1f - -# CHECK: fnmadd s1, s2, s3, s4 -# CHECK: fnmadd d1, d2, d3, d4 - -0x41 0x90 0x23 0x1f -0x41 0x90 0x63 0x1f - -# CHECK: fnmsub s1, s2, s3, s4 -# CHECK: fnmsub d1, d2, d3, d4 - -0x41 0x88 0x23 0x1e -0x41 0x88 0x63 0x1e - -# CHECK: fnmul s1, s2, s3 -# CHECK: fnmul d1, d2, d3 - -0x41 0xc0 0x21 0x1e -0x41 0xc0 0x61 0x1e - -# CHECK: fsqrt s1, s2 -# CHECK: fsqrt d1, d2 - -0x41 0x38 0x23 0x1e -0x41 0x38 0x63 0x1e - -# CHECK: fsub s1, s2, s3 -# CHECK: fsub d1, d2, d3 - -#----------------------------------------------------------------------------- -# Floating-point comparison -#----------------------------------------------------------------------------- - -0x20 0x04 0x22 0x1e -0x20 0x04 0x62 0x1e -0x30 0x04 0x22 0x1e -0x30 0x04 0x62 0x1e - -# CHECK: fccmp s1, s2, #0, eq -# CHECK: fccmp d1, d2, #0, eq -# CHECK: fccmpe s1, s2, #0, eq -# CHECK: fccmpe d1, d2, #0, eq - -0x20 0x20 0x22 0x1e -0x20 0x20 0x62 0x1e -0x28 0x20 0x20 0x1e -0x28 0x20 0x60 0x1e -0x30 0x20 0x22 0x1e -0x30 0x20 0x62 0x1e -0x38 0x20 0x20 0x1e -0x38 0x20 0x60 0x1e - -# CHECK: fcmp s1, s2 -# CHECK: fcmp d1, d2 -# CHECK: fcmp s1, #0.0 -# CHECK: fcmp d1, #0.0 -# CHECK: fcmpe s1, s2 -# CHECK: fcmpe d1, d2 -# CHECK: fcmpe s1, #0.0 -# CHECK: fcmpe d1, #0.0 - -#----------------------------------------------------------------------------- -# Floating-point conditional select -#----------------------------------------------------------------------------- - -0x41 0x0c 0x23 0x1e -0x41 0x0c 0x63 0x1e - -# CHECK: fcsel s1, s2, s3, eq -# CHECK: fcsel d1, d2, d3, eq - -#----------------------------------------------------------------------------- -# Floating-point convert -#----------------------------------------------------------------------------- - -0x41 0xc0 0x63 0x1e -0x41 0x40 0x62 0x1e -0x41 0xc0 0xe2 0x1e -0x41 0x40 0xe2 0x1e -0x41 0xc0 0x22 0x1e -0x41 0xc0 0x23 0x1e - -# CHECK: fcvt h1, d2 -# CHECK: fcvt s1, d2 -# CHECK: fcvt d1, h2 -# CHECK: fcvt s1, h2 -# CHECK: fcvt d1, s2 -# CHECK: fcvt h1, s2 - -0x41 0x00 0x44 0x1e -0x41 0x04 0x44 0x1e -0x41 0x00 0x44 0x9e -0x41 0x04 0x44 0x9e -0x41 0x00 0x04 0x1e -0x41 0x04 0x04 0x1e -0x41 0x00 0x04 0x9e -0x41 0x04 0x04 0x9e - -#----------------------------------------------------------------------------- -# Floating-point move -#----------------------------------------------------------------------------- - -0x41 0x00 0x27 0x1e -0x41 0x00 0x26 0x1e -0x41 0x00 0x67 0x9e -0x41 0x00 0x66 0x9e - -# CHECK: fmov s1, w2 -# CHECK: fmov w1, s2 -# CHECK: fmov d1, x2 -# CHECK: fmov x1, d2 - -0x01 0x10 0x28 0x1e -0x01 0x10 0x68 0x1e -0x01 0xf0 0x7b 0x1e -0x01 0xf0 0x6b 0x1e - -# CHECK: fmov s1, #0.12500000 -# CHECK: fmov d1, #0.12500000 -# CHECK: fmov d1, #-0.48437500 -# CHECK: fmov d1, #0.48437500 - -0x41 0x40 0x20 0x1e -0x41 0x40 0x60 0x1e - -# CHECK: fmov s1, s2 -# CHECK: fmov d1, d2 - -#----------------------------------------------------------------------------- -# Floating-point round to integral -#----------------------------------------------------------------------------- - -0x41 0x40 0x26 0x1e -0x41 0x40 0x66 0x1e - -# CHECK: frinta s1, s2 -# CHECK: frinta d1, d2 - -0x41 0xc0 0x27 0x1e -0x41 0xc0 0x67 0x1e - -# CHECK: frinti s1, s2 -# CHECK: frinti d1, d2 - -0x41 0x40 0x25 0x1e -0x41 0x40 0x65 0x1e - -# CHECK: frintm s1, s2 -# CHECK: frintm d1, d2 - -0x41 0x40 0x24 0x1e -0x41 0x40 0x64 0x1e - -# CHECK: frintn s1, s2 -# CHECK: frintn d1, d2 - -0x41 0xc0 0x24 0x1e -0x41 0xc0 0x64 0x1e - -# CHECK: frintp s1, s2 -# CHECK: frintp d1, d2 - -0x41 0x40 0x27 0x1e -0x41 0x40 0x67 0x1e - -# CHECK: frintx s1, s2 -# CHECK: frintx d1, d2 - -0x41 0xc0 0x25 0x1e -0x41 0xc0 0x65 0x1e - -# CHECK: frintz s1, s2 -# CHECK: frintz d1, d2 - - 0x00 0x3c 0xe0 0x7e - 0x00 0x8c 0xe0 0x5e - -# CHECK: cmhs d0, d0, d0 -# CHECK: cmtst d0, d0, d0 - -0x00 0x00 0xaf 0x9e -0x00 0x00 0xae 0x9e - -# CHECK: fmov.d v0[1], x0 -# CHECK: fmov.d x0, v0[1] - diff --git a/llvm/test/MC/Disassembler/ARM64/system.txt b/llvm/test/MC/Disassembler/ARM64/system.txt deleted file mode 100644 index 9027a60dd30..00000000000 --- a/llvm/test/MC/Disassembler/ARM64/system.txt +++ /dev/null @@ -1,62 +0,0 @@ -# RUN: llvm-mc -triple arm64-apple-darwin --disassemble < %s | FileCheck %s - - -#----------------------------------------------------------------------------- -# Hint encodings -#----------------------------------------------------------------------------- - - 0x1f 0x20 0x03 0xd5 -# CHECK: nop - 0x9f 0x20 0x03 0xd5 -# CHECK: sev - 0xbf 0x20 0x03 0xd5 -# CHECK: sevl - 0x5f 0x20 0x03 0xd5 -# CHECK: wfe - 0x7f 0x20 0x03 0xd5 -# CHECK: wfi - 0x3f 0x20 0x03 0xd5 -# CHECK: yield - -#----------------------------------------------------------------------------- -# Single-immediate operand instructions -#----------------------------------------------------------------------------- - - 0x5f 0x3a 0x03 0xd5 -# CHECK: clrex #10 - 0xdf 0x3f 0x03 0xd5 -# CHECK: isb{{$}} - 0xdf 0x31 0x03 0xd5 -# CHECK: isb #1 - 0xbf 0x33 0x03 0xd5 -# CHECK: dmb osh - 0x9f 0x37 0x03 0xd5 -# CHECK: dsb nsh - 0x3f 0x76 0x08 0xd5 -# CHECK: dc ivac - -#----------------------------------------------------------------------------- -# Generic system instructions -#----------------------------------------------------------------------------- - 0xff 0x05 0x0a 0xd5 - 0xe7 0x6a 0x0f 0xd5 - 0xf4 0x3f 0x2e 0xd5 - 0xbf 0x40 0x00 0xd5 - 0x00 0xb0 0x18 0xd5 - 0x00 0xb0 0x38 0xd5 - -# CHECK: sys #2, c0, c5, #7 -# CHECK: sys #7, c6, c10, #7, x7 -# CHECK: sysl x20, #6, c3, c15, #7 -# CHECK: msr SPSEL, #0 -# CHECK: msr S3_0_C11_C0_0, x0 -# CHECK: mrs x0, S3_0_C11_C0_0 - - 0x40 0xc0 0x1e 0xd5 - 0x40 0xc0 0x1c 0xd5 - 0x40 0xc0 0x18 0xd5 - -# CHECK: msr RMR_EL3, x0 -# CHECK: msr RMR_EL2, x0 -# CHECK: msr RMR_EL1, x0 - |
