summaryrefslogtreecommitdiffstats
path: root/llvm/test/MC/Disassembler/ARM64
Commit message (Collapse)AuthorAgeFilesLines
* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-2415-4152/+0
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* TableGen: fix operand counting for aliasesTim Northover2014-05-161-4/+4
| | | | | | | | | | | | | | | | | | | | | TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
* ARM64: print correct aliases for NEON mov & mvn instructionsTim Northover2014-05-151-5/+5
| | | | | | | | In all cases, if a "mov" alias exists, it is the canonical form of the instruction. Now that TableGen can support aliases containing syntax variants, we can enable them and improve the quality of the asm output. llvm-svn: 208874
* TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover2014-05-151-2/+2
| | | | | | | To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
* AArch64/ARM64: print BFM instructions as BFI or BFXILTim Northover2014-05-011-2/+2
| | | | | | | The canonical form of the BFM instruction is always one of the more explicit extract or insert operations, which makes reading output much easier. llvm-svn: 207752
* ARM64: print fp immediates without using scientific notation.Tim Northover2014-04-302-7/+7
| | | | llvm-svn: 207669
* ARM64: print lsr instead of lsrv for variable shifts (etc)Tim Northover2014-04-301-8/+8
| | | | | | | The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
* ARM64: use hex immediates for movz/movk instructionsTim Northover2014-04-301-12/+12
| | | | | | | | Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to piece together an immediate in 16-bit chunks, hex is probably the most appropriate format. llvm-svn: 207635
* ARM64: hexify printing various immediate operandsTim Northover2014-04-302-64/+63
| | | | | | | | | | This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they accept weird shifts which are more naturally understandable in hex notation). Also changes BRK/HINT etc, which is probably a neutral change, but easier than the alternative. llvm-svn: 207634
* ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover2014-04-301-8/+8
| | | | | | | | | | Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. llvm-svn: 207633
* [ARM64] Print preferred aliases for SFBM/UBFM in InstPrinterBradley Smith2014-04-251-4/+4
| | | | llvm-svn: 207219
* [ARM64] Support crc predicate on ARM64.Kevin Qin2014-04-251-1/+1
| | | | | | | According to the specification, CRC is an optional extension of the architecture. llvm-svn: 207214
* [ARM64] Enable feature predicates for NEON / FP / CRYPTO.Kevin Qin2014-04-235-6/+6
| | | | | | | | AArch64 has feature predicates for NEON, FP and CRYPTO instructions. This allows the compiler to generate code without using FP, NEON or CRYPTO instructions. llvm-svn: 206949
* [ARM64] Change SYS without a register to an alias to make disassembling more ↵Bradley Smith2014-04-091-0/+2
| | | | | | consistant. llvm-svn: 205898
* [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.Bradley Smith2014-04-091-0/+2
| | | | llvm-svn: 205897
* [ARM64] Properly support both apple and standard syntax for FMOVBradley Smith2014-04-092-1/+8
| | | | llvm-svn: 205896
* [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.Bradley Smith2014-04-092-0/+10
| | | | llvm-svn: 205895
* [ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.Bradley Smith2014-04-091-3/+7
| | | | llvm-svn: 205893
* [ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.Bradley Smith2014-04-091-0/+4
| | | | llvm-svn: 205890
* [ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a ↵Bradley Smith2014-04-091-0/+4
| | | | | | dumb alias. llvm-svn: 205889
* [ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.Bradley Smith2014-04-091-0/+2
| | | | llvm-svn: 205887
* [ARM64] Rename LR to the UAL-compliant 'X30'.Bradley Smith2014-04-091-4/+4
| | | | llvm-svn: 205885
* [ARM64] Rename FP to the UAL-compliant 'X29'.Bradley Smith2014-04-091-4/+4
| | | | llvm-svn: 205884
* [ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be ↵Bradley Smith2014-04-091-0/+4
| | | | | | zero but should be decoded/disassembled with any value. llvm-svn: 205883
* [ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.Bradley Smith2014-04-091-0/+5
| | | | llvm-svn: 205882
* [ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have ↵Bradley Smith2014-04-091-0/+3
| | | | | | the top bit of their immediate clear. llvm-svn: 205881
* [ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.Bradley Smith2014-04-091-0/+2
| | | | llvm-svn: 205879
* [ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.Bradley Smith2014-04-091-0/+4
| | | | llvm-svn: 205877
* [ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and ↵Bradley Smith2014-04-091-0/+5
| | | | | | stores, so the unused register fields are set to all-ones canonically but are recognised with any value. llvm-svn: 205874
* [ARM64] Move CPSRField and DBarrier operands over to AArch64-style ↵Bradley Smith2014-04-091-1/+1
| | | | | | disassembly and assembly. This removes the last users of namespace ARM64SYS. llvm-svn: 205869
* [ARM64] Switch the decoder, disassembler, instprinter and asmparser over to ↵Bradley Smith2014-04-091-6/+6
| | | | | | using AArch64-style system registers, and fix up test failures discovered in the process. llvm-svn: 205868
* [ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and ↵Bradley Smith2014-04-092-24/+29
| | | | | | also (for add/sub only) if shift=11. llvm-svn: 205865
* [ARM64] STRHro and STRBro were not being decoded at all.Bradley Smith2014-04-091-0/+2
| | | | llvm-svn: 205860
* [ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB ↵Bradley Smith2014-04-091-1/+10
| | | | | | instructions is unallocated if shift > 4. llvm-svn: 205859
* [ARM64] Register-offset loads and stores with the 'option' field equal to ↵Bradley Smith2014-04-091-0/+7
| | | | | | 00x or 10x are undefined. llvm-svn: 205858
* ARM64: initial backend importTim Northover2014-03-2912-0/+4072
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
OpenPOWER on IntegriCloud