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path: root/llvm/test/MC/Disassembler/ARM/thumb-tests.txt
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* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-141-3/+6
* Reverting, broke some bots. Need further investigation.Diogo Sampaio2020-01-101-6/+3
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-101-3/+6
* Remove the cortex-a9-mp CPU.Charlie Turner2014-11-031-1/+1
* This fixes the Thumb2 CPS assembly syntax.Mihai Popa2013-08-091-1/+1
* ARM: fix thumb coprocessor instruction with pre-writeback disassemblyAmaury de la Vieuville2013-06-141-0/+3
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-301-1/+1
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-0/+8
* Specify cpu to unbreak tests.Evan Cheng2012-04-261-1/+1
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-121-1/+1
* Check in a patch that has already been code reviewed by Owen that I'd forgott...James Molloy2011-09-281-0/+6
* Fix incorrect disassembly test.Owen Anderson2011-09-231-1/+1
* Print out immediate offset versions of PC-relative load/store instructions as...Owen Anderson2011-09-211-1/+1
* Create Thumb2 versions of STC/LDC, and reenable the relevant tests.Owen Anderson2011-09-071-5/+2
* Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds p...James Molloy2011-09-071-3/+6
* Update test for 139243Jim Grosbach2011-09-071-1/+1
* Fix decoding of Thumb2 prefetch instructions, which account for all the remai...Owen Anderson2011-08-231-0/+3
* Fix two more instances of mis-matched operand names breaking disassembly. Fo...Owen Anderson2011-08-231-0/+6
* t2SMLAD is a four-register instruction, not a three-register one.Owen Anderson2011-08-221-0/+3
* Correct operand naming of t2USAT16 to allow proper decoding.Owen Anderson2011-08-221-0/+3
* Match operand naming to allow correct decoding of t2LDRSH_POST.Owen Anderson2011-08-221-0/+3
* Provide a correct decoder hook for Thumb2 shifted registers. Found by random...Owen Anderson2011-08-221-0/+3
* Thumb assembly parsing and encoding for LDM instruction.Jim Grosbach2011-08-181-5/+5
* Add a test for Thumb1 LDRSH decoding.Owen Anderson2011-08-151-0/+3
* Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.Owen Anderson2011-08-151-0/+3
* Add initial support for decoding NEON instructions in Thumb2 mode.Owen Anderson2011-08-101-0/+3
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-191-1/+1
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immedi...Johnny Chen2011-05-181-0/+3
* Add tests for A8.6.110 NOP.Johnny Chen2011-04-271-0/+6
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) s...Johnny Chen2011-04-221-0/+3
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-151-0/+3
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of opera...Johnny Chen2011-04-141-0/+3
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-0/+3
* Check for unallocated instruction encodings when disassembling Thumb Branch i...Johnny Chen2011-04-131-2/+2
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was no...Johnny Chen2011-04-131-0/+3
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-0/+3
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have it...Johnny Chen2011-04-121-1/+13
* Add one test case (svc).Johnny Chen2011-04-121-0/+3
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-0/+9
* Fix the bug where the immediate shift amount for Thumb logical shift instruct...Johnny Chen2011-04-111-0/+6
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-081-0/+6
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-061-0/+3
* ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen2011-04-051-2/+2
* Add a test case for thumb stc2 instruction.Johnny Chen2011-03-301-0/+3
* Fixed the t2PLD and friends disassembly and add two test cases.Johnny Chen2011-03-261-0/+6
* Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt.Johnny Chen2011-03-251-0/+3
* Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul().Johnny Chen2011-03-251-0/+6
* Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegC...Johnny Chen2011-03-251-0/+9
* DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to RegCl...Johnny Chen2011-03-251-0/+6
* A8.6.226 TBB, TBH:Johnny Chen2011-03-251-0/+6
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