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* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-144-8/+18
* Reverting, broke some bots. Need further investigation.Diogo Sampaio2020-01-104-18/+8
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-104-8/+18
* [MC][ARM] vscclrm disassembles as vldmiaAlexandros Lamprineas2019-09-271-1/+4
* [ARM] Remove some spurious MVE reduction instructions.Simon Tatham2019-09-091-1/+38
* [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodingsOliver Stannard2019-09-091-0/+42
* [ARM][MVE] Decoding of VMSR doesn't diagnose some unpredictable encodingsOliver Stannard2019-09-031-0/+178
* [ARM] Reject CSEL instructions with invalid operandsMikhail Maltsev2019-07-311-13/+12
* [ARM] Add <saturate> operand to SQRSHRL and UQRSHLLMikhail Maltsev2019-07-191-2/+10
* [ARM] Remove nonexistent unsigned forms of MVE VQDMLAH.Simon Tatham2019-07-111-13/+14
* [ARM] Fix handling of zero offsets in LOB instructions.Simon Tatham2019-06-273-25/+47
* [ARM] Make coprocessor number restrictions consistent.Simon Tatham2019-06-272-0/+138
* [ARM] Tighten restrictions on use of SP in v8.1-M CSEL.Simon Tatham2019-06-272-2/+16
* [ARM] Extra MVE-related testing.Simon Tatham2019-06-251-0/+3
* [ARM] Add remaining miscellaneous MVE instructions.Simon Tatham2019-06-251-0/+111
* [ARM] Add MVE vector load/store instructions.Simon Tatham2019-06-251-0/+1378
* [ARM] Add MVE interleaving load/store family.Simon Tatham2019-06-241-0/+267
* [ARM] Add MVE 64-bit GPR <-> vector move instructions.Simon Tatham2019-06-211-0/+20
* [ARM] Add MVE vector instructions that take a scalar input.Simon Tatham2019-06-211-0/+531
* [ARM] Add a batch of similarly encoded MVE instructions.Simon Tatham2019-06-211-0/+391
* [ARM] Add MVE vector compare instructions.Simon Tatham2019-06-211-0/+179
* [ARM] Add a batch of MVE floating-point instructions.Simon Tatham2019-06-211-0/+195
* [ARM] Add a batch of MVE integer instructions.Simon Tatham2019-06-201-0/+401
* [ARM] Add MVE vector bit-operations (register inputs).Simon Tatham2019-06-192-0/+163
* [ARM] Add MVE vector shift instructions.Simon Tatham2019-06-181-0/+585
* [ARM] Add MVE integer vector min/max instructions.Simon Tatham2019-06-181-0/+48
* [lit] Delete empty lines at the end of lit.local.cfg NFCFangrui Song2019-06-171-1/+0
* [ARM] Add MVE horizontal accumulation instructionsMikhail Maltsev2019-06-141-0/+212
* [ARM] Set up infrastructure for MVE vector instructions.Simon Tatham2019-06-133-0/+51
* [ARM] Fix a typo in the test from r363039Ilya Biryukov2019-06-111-1/+1
* [ARM] First MVE instructions: scalar shifts.Mikhail Maltsev2019-06-111-0/+83
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-116-0/+1734
* Revert rL362953 and its followup rL362955.Simon Tatham2019-06-106-1734/+0
* [ARM] Add the non-MVE instructions in Arm v8.1-M.Simon Tatham2019-06-106-0/+1734
* [ARM] Turn some undefined encoding bits into 0s.Simon Tatham2019-06-041-0/+92
* ARM: disallow add/sub to sp unless Rn is also sp.Tim Northover2019-04-231-0/+31
* [ARM][MC] Update one test case in 'test/MC/Disassembler/ARM/invalid-armv7.txt'Xing GUO2019-03-051-3/+3
* [ARM] Make fullfp16 instructions not conditionalisable.Simon Tatham2019-02-252-0/+15
* [NFC] Fix missing testfile change of rL350299Diogo N. Sampaio2019-01-031-2/+2
* [ARM] Add command-line option for SBDiogo N. Sampaio2019-01-032-9/+9
* [ARM][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-282-4/+4
* [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction setsOliver Stannard2018-09-272-0/+18
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-172-0/+146
* [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instructionSjoerd Meijer2018-07-062-0/+20
* ARM: correctly decode VFP instructions following unpredictable t2ITTim Northover2018-06-261-6/+6
* [ARM]Decoding MSR with unpredictable destination register causes an assertSimi Pallipurath2018-03-061-4/+4
* [ARM] Re-commit r324600 with fixed LLVMBuild.txtOliver Stannard2018-02-082-2/+33
* Revert r324600 as it breaks a buildbotOliver Stannard2018-02-082-33/+2
* [ARM] Fix disassembly of invalid banked register movesOliver Stannard2018-02-082-2/+33
* [ARM][AArch64] Add CSDB speculation barrier instructionOliver Stannard2018-02-062-0/+8
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