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* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-141-3/+6
| | | | | | | | | | | | | | | | | | | | Summary: This patch fixes pr23772 [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80". The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable. To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP). Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations. When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant ) It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt). Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb Reviewed By: efriedma Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70680
* Reverting, broke some bots. Need further investigation.Diogo Sampaio2020-01-101-6/+3
| | | | | | | | Summary: This reverts commit 8c12769f3046029e2a9b4e48e1645b1a77d28650. Reviewers: Subscribers:
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-101-3/+6
| | | | | | | | | | | | | | | | | | | | Summary: This patch fixes pr23772 [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80". The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable. To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP). Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations. When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant ) It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt). Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma Reviewed By: efriedma Subscribers: john.brawn, efriedma, ostannard, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70680
* Remove the cortex-a9-mp CPU.Charlie Turner2014-11-031-1/+1
| | | | | | | | | | | | | | | | | | This CPU definition is redundant. The Cortex-A9 is defined as supporting multiprocessing extensions. Remove its definition and update appropriate tests. LLVM defines both a cortex-a9 CPU and a cortex-a9-mp CPU. The only difference between the two CPU definitions in ARM.td is that cortex-a9-mp contains the feature FeatureMP for multiprocessing extensions. This is redundant since the Cortex-A9 is defined as having multiprocessing extensions in the TRMs. armcc also defines the Cortex-A9 as having multiprocessing extensions by default. Change-Id: Ifcadaa6c322be0a33d9d2a39cfdd7da1d75981a7 llvm-svn: 221166
* This fixes the Thumb2 CPS assembly syntax.Mihai Popa2013-08-091-1/+1
| | | | | | | | | | | | | | In Thumb1, only one variant is supported: CPS{effect} {flags} Thumb2 supports three: CPS{effect}.W {flags} CPS{effect} {flags} {mode} CPS {mode} Canonically, .W should be used only when ambiguity is present between encodings of different width. The wide suffix is still accepted for the latter two forms via aliases. llvm-svn: 188071
* ARM: fix thumb coprocessor instruction with pre-writeback disassemblyAmaury de la Vieuville2013-06-141-0/+3
| | | | | | | was stc2 p0, c0, [r0]! instead of stc2 p0, c0, [r0,#0]! llvm-svn: 183975
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-301-1/+1
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 llvm-svn: 166991
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-0/+8
| | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! llvm-svn: 156118
* Specify cpu to unbreak tests.Evan Cheng2012-04-261-1/+1
| | | | llvm-svn: 155604
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-121-1/+1
| | | | llvm-svn: 141811
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-281-0/+6
| | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
* Fix incorrect disassembly test.Owen Anderson2011-09-231-1/+1
| | | | llvm-svn: 140423
* Print out immediate offset versions of PC-relative load/store instructions ↵Owen Anderson2011-09-211-1/+1
| | | | | | as [pc, #123] rather than simply #123. llvm-svn: 140283
* Create Thumb2 versions of STC/LDC, and reenable the relevant tests.Owen Anderson2011-09-071-5/+2
| | | | llvm-svn: 139256
* Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds ↵James Molloy2011-09-071-3/+6
| | | | | | predicate checking to the Disassembler. llvm-svn: 139250
* Update test for 139243Jim Grosbach2011-09-071-1/+1
| | | | llvm-svn: 139244
* Fix decoding of Thumb2 prefetch instructions, which account for all the ↵Owen Anderson2011-08-231-0/+3
| | | | | | remaining Thumb2 decoding failures found by randomized testing so far. llvm-svn: 138341
* Fix two more instances of mis-matched operand names breaking disassembly. ↵Owen Anderson2011-08-231-0/+6
| | | | | | Found by randomized testing. llvm-svn: 138337
* t2SMLAD is a four-register instruction, not a three-register one.Owen Anderson2011-08-221-0/+3
| | | | llvm-svn: 138301
* Correct operand naming of t2USAT16 to allow proper decoding.Owen Anderson2011-08-221-0/+3
| | | | llvm-svn: 138300
* Match operand naming to allow correct decoding of t2LDRSH_POST.Owen Anderson2011-08-221-0/+3
| | | | llvm-svn: 138298
* Provide a correct decoder hook for Thumb2 shifted registers. Found by ↵Owen Anderson2011-08-221-0/+3
| | | | | | randomized testing. llvm-svn: 138292
* Thumb assembly parsing and encoding for LDM instruction.Jim Grosbach2011-08-181-5/+5
| | | | | | | | Fix base register type and canonicallize to the "ldm" spelling rather than "ldmia." Add diagnostics for incorrect writeback token and out-of-range registers. llvm-svn: 137986
* Add a test for Thumb1 LDRSH decoding.Owen Anderson2011-08-151-0/+3
| | | | llvm-svn: 137645
* Fix decoding LDRSB and LDRSH in Thumb1 mode. Patch by James Molloy.Owen Anderson2011-08-151-0/+3
| | | | llvm-svn: 137636
* Add initial support for decoding NEON instructions in Thumb2 mode.Owen Anderson2011-08-101-0/+3
| | | | llvm-svn: 137236
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-191-1/+1
| | | | | | | | The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. llvm-svn: 135532
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' ↵Johnny Chen2011-05-181-0/+3
| | | | | | immediate operand. llvm-svn: 131565
* Add tests for A8.6.110 NOP.Johnny Chen2011-04-271-0/+6
| | | | llvm-svn: 130345
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) ↵Johnny Chen2011-04-221-0/+3
| | | | | | | | | | should print out ldr, not ldr.n. rdar://problem/9267772 llvm-svn: 130008
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-151-0/+3
| | | | | | rdar://problem/9292717 llvm-svn: 129619
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of ↵Johnny Chen2011-04-141-0/+3
| | | | | | operations. llvm-svn: 129531
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-0/+3
| | | | | | rdar://problem/9280370 llvm-svn: 129480
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-131-2/+2
| | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 llvm-svn: 129471
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-0/+3
| | | | | | | | not properly handled. rdar://problem/9276427 llvm-svn: 129456
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-0/+3
| | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 llvm-svn: 129391
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have ↵Johnny Chen2011-04-121-1/+13
| | | | | | | | | | its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. llvm-svn: 129377
* Add one test case (svc).Johnny Chen2011-04-121-0/+3
| | | | llvm-svn: 129327
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-0/+9
| | | | | | rdar://problem/9267838 llvm-svn: 129320
* Fix the bug where the immediate shift amount for Thumb logical shift ↵Johnny Chen2011-04-111-0/+6
| | | | | | | | instructions are incorrectly disassembled. rdar://problem/9266265 llvm-svn: 129298
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-081-0/+6
| | | | | | | PR9648 rdar://problem/9257634 llvm-svn: 129146
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-061-0/+3
| | | | | | | | | | Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 llvm-svn: 129027
* ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.Johnny Chen2011-04-051-2/+2
| | | | llvm-svn: 128913
* Add a test case for thumb stc2 instruction.Johnny Chen2011-03-301-0/+3
| | | | llvm-svn: 128517
* Fixed the t2PLD and friends disassembly and add two test cases.Johnny Chen2011-03-261-0/+6
| | | | llvm-svn: 128322
* Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt.Johnny Chen2011-03-251-0/+3
| | | | llvm-svn: 128306
* Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul().Johnny Chen2011-03-251-0/+6
| | | | llvm-svn: 128305
* Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode ↵Johnny Chen2011-03-251-0/+9
| | | | | | | | | | GPRRegClassID. Also add some test cases. rdar://problem/9189829 llvm-svn: 128304
* DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to ↵Johnny Chen2011-03-251-0/+6
| | | | | | | | RegClass. Add two test cases. rdar://problem/9182892 llvm-svn: 128299
* A8.6.226 TBB, TBH:Johnny Chen2011-03-251-0/+6
| | | | | | Add two test cases. llvm-svn: 128295
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