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* [AArch64][v8.3a] Don't emit LDRA '[xN]!' alias in disassembly.Simon Tatham2019-11-281-2/+2
* [AArch64][v8.3a] Add LDRA '[xN]!' alias.Ahmed Bougacha2019-11-131-8/+14
* [AArch64] Adding support for PMMIR_EL1 registerVictor Campos2019-10-181-0/+10
* [AArch64,Assembler] Compiler support for ID_MMFR5_EL1Mark Murray2019-10-161-0/+2
* [AArch64InstPrinter] prefer bfi to bfc for < armv8.2-aNick Desaulniers2019-10-031-2/+5
* [AArch64] Update MTE system register encodingsLuke Cheeseman2019-08-211-20/+20
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-311-0/+19
* [AArch64] Define ETE and TRBE system registersMomchil Velikov2019-07-262-0/+71
* [ARM][AArch64] Support for Cortex-A65 & A65AE, Neoverse E1 & N1Pablo Barrio2019-07-251-3/+6
* Revert [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-171-19/+0
* [AArch64] Add support for Transactional Memory Extension (TME)Momchil Velikov2019-07-171-0/+19
* [lit] Delete empty lines at the end of lit.local.cfg NFCFangrui Song2019-06-171-1/+0
* [AArch64] Update v8.5a MTE LDG/STG instructionsJaved Absar2019-04-031-96/+145
* [AArch64] Add v8.5-a Memory Tagging STZGM instructionDavid Spickett2019-04-011-0/+12
* [AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructionsDavid Spickett2019-04-012-13/+6
* [AArch64] Add v8.5-a Memory Tagging GMID_EL1 registerDavid Spickett2019-04-011-0/+7
* [AArch64] Add support for Cortex-A76 and Cortex-A76AELuke Cheeseman2019-02-251-0/+2
* [AArch64] Move feature predctrl to predresDiogo N. Sampaio2019-01-091-2/+2
* [AArch64] Add command-line option for SBDiogo N. Sampaio2018-12-282-9/+9
* [AArch64] Add command-line option for SSBSPablo Barrio2018-12-032-10/+13
* [AArch64] Support HiSilicon's TSV110 processorBryan Chan2018-11-091-0/+1
* [FIX][AArch64] Add support for UDF instructionDiogo N. Sampaio2018-10-301-5/+3
* [FIX][AArch64] Add support for UDF instructionDiogo N. Sampaio2018-10-301-17/+5
* [AArch64] Add support for UDF instructionDiogo N. Sampaio2018-10-301-0/+30
* [AArch64][v8.5A] Add Memory Tagging instructionsOliver Stannard2018-10-022-3/+455
* [AArch64][v8.5A] Add Memory Tagging system registersOliver Stannard2018-10-021-2/+42
* [AArch64][v8.5A] Add MTE system instructionsOliver Stannard2018-10-021-0/+60
* [AArch64][v8.5A] Add speculation barriers SSBB and PSSBBOliver Stannard2018-09-272-3/+6
* [AArch64][v8.5A] Add Branch Target Identification instructionsOliver Stannard2018-09-271-0/+18
* [AArch64][v8.5A] Add speculation restriction system registersOliver Stannard2018-09-271-0/+52
* [AArch64][v8.5A] Add Armv8.5-A random number instructionsOliver Stannard2018-09-271-0/+12
* [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instructionOliver Stannard2018-09-271-0/+7
* [AArch64][v8.5A] Add prediction invalidation instructions to AArch64Oliver Stannard2018-09-271-0/+15
* [AArch64][v8.5A] Add speculation barrier to AArch64 instruction setOliver Stannard2018-09-271-0/+9
* [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructionsOliver Stannard2018-09-271-5/+94
* [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlagOliver Stannard2018-09-271-0/+12
* [ARM/AArch64] Support FP16 +fp16fml instructionsBernard Ogden2018-08-172-0/+182
* [AArch64] Armv8.2-A: add the crypto extensionsSjoerd Meijer2018-07-261-0/+93
* Follow up of r336913: forgot to add the new test files.Sjoerd Meijer2018-07-121-0/+277
* [AArch64] Armv8.4-A: TLB supportSjoerd Meijer2018-07-061-0/+151
* Recommit: [AArch64] Armv8.4-A: Flag manipulation instructionsSjoerd Meijer2018-07-061-0/+11
* Revert [AArch64] Armv8.4-A: Flag manipulation instructionsSjoerd Meijer2018-07-061-11/+0
* [AArch64] Armv8.4-A: Flag manipulation instructionsSjoerd Meijer2018-07-061-0/+11
* [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instructionSjoerd Meijer2018-07-061-0/+3
* [AArch64] Armv8.4-A: system registersSjoerd Meijer2018-07-036-0/+451
* [AArch64] Armv8.4-A: Virtualization system registersSjoerd Meijer2018-06-291-0/+39
* [AArch64] Fix spelling of ICH_ELRSR_EL2 system registerOliver Stannard2018-02-061-1/+1
* [ARM][AArch64] Add CSDB speculation barrier instructionOliver Stannard2018-02-061-0/+4
* [AArch64] CCSIDR2 system registerSam Parker2017-12-201-0/+3
* [AArch64][TableGen] Skip tied result operands for InstAliasSander de Smalen2017-11-201-24/+24
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