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| author | Oliver Stannard <oliver.stannard@arm.com> | 2018-09-27 14:05:46 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2018-09-27 14:05:46 +0000 |
| commit | 8459d34e820b0461f0c8f95b1c5add84e089ff1e (patch) | |
| tree | c5f012d7c4802c4c7fe1d76a2fc50d5d68eb8179 /llvm/test/MC/Disassembler/AArch64 | |
| parent | dc837e3f1f39aaff0f7c566602d03203d4b94fe4 (diff) | |
| download | bcm5719-llvm-8459d34e820b0461f0c8f95b1c5add84e089ff1e.tar.gz bcm5719-llvm-8459d34e820b0461f0c8f95b1c5add84e089ff1e.zip | |
[AArch64][v8.5A] Add speculation restriction system registers
This adds some new system registers which can be used to restrict
certain types of speculative execution.
Patch by Pablo Barrio and David Spickett!
Differential revision: https://reviews.llvm.org/D52482
llvm-svn: 343218
Diffstat (limited to 'llvm/test/MC/Disassembler/AArch64')
| -rw-r--r-- | llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt b/llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt new file mode 100644 index 00000000000..c26ab94630a --- /dev/null +++ b/llvm/test/MC/Disassembler/AArch64/armv8.5a-specrestrict.txt @@ -0,0 +1,52 @@ +# RUN: llvm-mc -triple=aarch64 -mattr=+specrestrict -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=-specrestrict -disassemble < %s | FileCheck %s --check-prefix=NOSPECID + +[0x81 0x03 0x38 0xd5] + +# CHECK: mrs x1, {{id_pfr2_el1|ID_PFR2_EL1}} +# NOSPECID: mrs x1, S3_0_C0_C3_4 + +[0xe8 0xd0 0x3b 0xd5] +[0xe7 0xd0 0x38 0xd5] +[0xe6 0xd0 0x3c 0xd5] +[0xe5 0xd0 0x3e 0xd5] +[0xe4 0xd0 0x3d 0xd5] + +# CHECK: mrs x8, {{scxtnum_el0|SCXTNUM_EL0}} +# CHECK: mrs x7, {{scxtnum_el1|SCXTNUM_EL1}} +# CHECK: mrs x6, {{scxtnum_el2|SCXTNUM_EL2}} +# CHECK: mrs x5, {{scxtnum_el3|SCXTNUM_EL3}} +# CHECK: mrs x4, {{scxtnum_el12|SCXTNUM_EL12}} +# NOSPECID: mrs x8, S3_3_C13_C0_7 +# NOSPECID: mrs x7, S3_0_C13_C0_7 +# NOSPECID: mrs x6, S3_4_C13_C0_7 +# NOSPECID: mrs x5, S3_6_C13_C0_7 +# NOSPECID: mrs x4, S3_5_C13_C0_7 + +[0xe8 0xd0 0x1b 0xd5] +[0xe7 0xd0 0x18 0xd5] +[0xe6 0xd0 0x1c 0xd5] +[0xe5 0xd0 0x1e 0xd5] +[0xe4 0xd0 0x1d 0xd5] + +# CHECK: msr {{scxtnum_el0|SCXTNUM_EL0}}, x8 +# CHECK: msr {{scxtnum_el1|SCXTNUM_EL1}}, x7 +# CHECK: msr {{scxtnum_el2|SCXTNUM_EL2}}, x6 +# CHECK: msr {{scxtnum_el3|SCXTNUM_EL3}}, x5 +# CHECK: msr {{scxtnum_el12|SCXTNUM_EL12}}, x4 +# NOSPECID: msr S3_3_C13_C0_7, x8 +# NOSPECID: msr S3_0_C13_C0_7, x7 +# NOSPECID: msr S3_4_C13_C0_7, x6 +# NOSPECID: msr S3_6_C13_C0_7, x5 +# NOSPECID: msr S3_5_C13_C0_7, x4 + +[0x3f 0x41 0x03 0xd5] +[0xc3 0x42 0x1b 0xd5] +[0xc2 0x42 0x3b 0xd5] +# CHECK: msr SSBS, #1 +# CHECK: msr SSBS, x3 +# CHECK: mrs x2, SSBS +# NOSPECID: msr S0_3_C4_C1_1, xzr +# NOSPECID: msr S3_3_C4_C2_6, x3 +# NOSPECID: mrs x2, S3_3_C4_C2_6 |
