[AArch64] Armv8.4-A: system registers

This adds the following system registers:
- RAS registers,
- MPAM registers,
- Activitiy monitor registers,
- Trace Extension registers,
- Timing insensitivity of data processing instructions,
- Enhanced Support for Nested Virtualization.

Differential Revision: https://reviews.llvm.org/D48871

llvm-svn: 336193

6 files changed, 451 insertions, 0 deletions

diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-actmon.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-actmon.txt
new file mode 100644
index 00000000000..5a17068c41f
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-actmon.txt
@@ -0,0 +1,277 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+[0x00,0xd2,0x1b,0xd5]
+[0x60,0xd2,0x1b,0xd5]
+[0x80,0xd2,0x1b,0xd5]
+[0xa0,0xd2,0x1b,0xd5]
+[0x00,0xd4,0x1b,0xd5]
+[0x20,0xd4,0x1b,0xd5]
+[0x40,0xd4,0x1b,0xd5]
+[0x60,0xd4,0x1b,0xd5]
+[0x00,0xd3,0x1b,0xd5]
+[0x20,0xd3,0x1b,0xd5]
+[0x00,0xdc,0x1b,0xd5]
+[0x20,0xdc,0x1b,0xd5]
+[0x40,0xdc,0x1b,0xd5]
+[0x60,0xdc,0x1b,0xd5]
+[0x80,0xdc,0x1b,0xd5]
+[0xa0,0xdc,0x1b,0xd5]
+[0xc0,0xdc,0x1b,0xd5]
+[0xe0,0xdc,0x1b,0xd5]
+[0x00,0xdd,0x1b,0xd5]
+[0x20,0xdd,0x1b,0xd5]
+[0x40,0xdd,0x1b,0xd5]
+[0x60,0xdd,0x1b,0xd5]
+[0x80,0xdd,0x1b,0xd5]
+[0xa0,0xdd,0x1b,0xd5]
+[0xc0,0xdd,0x1b,0xd5]
+[0xe0,0xdd,0x1b,0xd5]
+[0x00,0xde,0x1b,0xd5]
+[0x20,0xde,0x1b,0xd5]
+[0x40,0xde,0x1b,0xd5]
+[0x60,0xde,0x1b,0xd5]
+[0x80,0xde,0x1b,0xd5]
+[0xa0,0xde,0x1b,0xd5]
+[0xc0,0xde,0x1b,0xd5]
+[0xe0,0xde,0x1b,0xd5]
+[0x00,0xdf,0x1b,0xd5]
+[0x20,0xdf,0x1b,0xd5]
+[0x40,0xdf,0x1b,0xd5]
+[0x60,0xdf,0x1b,0xd5]
+[0x80,0xdf,0x1b,0xd5]
+[0xa0,0xdf,0x1b,0xd5]
+[0xc0,0xdf,0x1b,0xd5]
+[0xe0,0xdf,0x1b,0xd5]
+
+[0x00,0xd2,0x3b,0xd5]
+[0x20,0xd2,0x3b,0xd5]
+[0x40,0xd2,0x3b,0xd5]
+[0x60,0xd2,0x3b,0xd5]
+[0x80,0xd2,0x3b,0xd5]
+[0xa0,0xd2,0x3b,0xd5]
+[0x00,0xd4,0x3b,0xd5]
+[0x20,0xd4,0x3b,0xd5]
+[0x40,0xd4,0x3b,0xd5]
+[0x60,0xd4,0x3b,0xd5]
+[0x00,0xd6,0x3b,0xd5]
+[0x20,0xd6,0x3b,0xd5]
+[0x40,0xd6,0x3b,0xd5]
+[0x60,0xd6,0x3b,0xd5]
+[0x00,0xd3,0x3b,0xd5]
+[0x20,0xd3,0x3b,0xd5]
+[0x00,0xdc,0x3b,0xd5]
+[0x20,0xdc,0x3b,0xd5]
+[0x40,0xdc,0x3b,0xd5]
+[0x60,0xdc,0x3b,0xd5]
+[0x80,0xdc,0x3b,0xd5]
+[0xa0,0xdc,0x3b,0xd5]
+[0xc0,0xdc,0x3b,0xd5]
+[0xe0,0xdc,0x3b,0xd5]
+[0x00,0xdd,0x3b,0xd5]
+[0x20,0xdd,0x3b,0xd5]
+[0x40,0xdd,0x3b,0xd5]
+[0x60,0xdd,0x3b,0xd5]
+[0x80,0xdd,0x3b,0xd5]
+[0xa0,0xdd,0x3b,0xd5]
+[0xc0,0xdd,0x3b,0xd5]
+[0xe0,0xdd,0x3b,0xd5]
+[0x00,0xde,0x3b,0xd5]
+[0x20,0xde,0x3b,0xd5]
+[0x40,0xde,0x3b,0xd5]
+[0x60,0xde,0x3b,0xd5]
+[0x80,0xde,0x3b,0xd5]
+[0xa0,0xde,0x3b,0xd5]
+[0xc0,0xde,0x3b,0xd5]
+[0xe0,0xde,0x3b,0xd5]
+[0x00,0xdf,0x3b,0xd5]
+[0x20,0xdf,0x3b,0xd5]
+[0x40,0xdf,0x3b,0xd5]
+[0x60,0xdf,0x3b,0xd5]
+[0x80,0xdf,0x3b,0xd5]
+[0xa0,0xdf,0x3b,0xd5]
+[0xc0,0xdf,0x3b,0xd5]
+[0xe0,0xdf,0x3b,0xd5]
+
+#CHECK:  msr AMCR_EL0, x0
+#CHECK:  msr AMUSERENR_EL0, x0
+#CHECK:  msr AMCNTENCLR0_EL0, x0
+#CHECK:  msr AMCNTENSET0_EL0, x0
+#CHECK:  msr AMEVCNTR00_EL0, x0
+#CHECK:  msr AMEVCNTR01_EL0, x0
+#CHECK:  msr AMEVCNTR02_EL0, x0
+#CHECK:  msr AMEVCNTR03_EL0, x0
+#CHECK:  msr AMCNTENCLR1_EL0, x0
+#CHECK:  msr AMCNTENSET1_EL0, x0
+#CHECK:  msr AMEVCNTR10_EL0, x0
+#CHECK:  msr AMEVCNTR11_EL0, x0
+#CHECK:  msr AMEVCNTR12_EL0, x0
+#CHECK:  msr AMEVCNTR13_EL0, x0
+#CHECK:  msr AMEVCNTR14_EL0, x0
+#CHECK:  msr AMEVCNTR15_EL0, x0
+#CHECK:  msr AMEVCNTR16_EL0, x0
+#CHECK:  msr AMEVCNTR17_EL0, x0
+#CHECK:  msr AMEVCNTR18_EL0, x0
+#CHECK:  msr AMEVCNTR19_EL0, x0
+#CHECK:  msr AMEVCNTR110_EL0, x0
+#CHECK:  msr AMEVCNTR111_EL0, x0
+#CHECK:  msr AMEVCNTR112_EL0, x0
+#CHECK:  msr AMEVCNTR113_EL0, x0
+#CHECK:  msr AMEVCNTR114_EL0, x0
+#CHECK:  msr AMEVCNTR115_EL0, x0
+#CHECK:  msr AMEVTYPER10_EL0, x0
+#CHECK:  msr AMEVTYPER11_EL0, x0
+#CHECK:  msr AMEVTYPER12_EL0, x0
+#CHECK:  msr AMEVTYPER13_EL0, x0
+#CHECK:  msr AMEVTYPER14_EL0, x0
+#CHECK:  msr AMEVTYPER15_EL0, x0
+#CHECK:  msr AMEVTYPER16_EL0, x0
+#CHECK:  msr AMEVTYPER17_EL0, x0
+#CHECK:  msr AMEVTYPER18_EL0, x0
+#CHECK:  msr AMEVTYPER19_EL0, x0
+#CHECK:  msr AMEVTYPER110_EL0, x0
+#CHECK:  msr AMEVTYPER111_EL0, x0
+#CHECK:  msr AMEVTYPER112_EL0, x0
+#CHECK:  msr AMEVTYPER113_EL0, x0
+#CHECK:  msr AMEVTYPER114_EL0, x0
+#CHECK:  msr AMEVTYPER115_EL0, x0
+
+#CHECK:  mrs x0, AMCR_EL0
+#CHECK:  mrs x0, AMCFGR_EL0
+#CHECK:  mrs x0, AMCGCR_EL0
+#CHECK:  mrs x0, AMUSERENR_EL0
+#CHECK:  mrs x0, AMCNTENCLR0_EL0
+#CHECK:  mrs x0, AMCNTENSET0_EL0
+#CHECK:  mrs x0, AMEVCNTR00_EL0
+#CHECK:  mrs x0, AMEVCNTR01_EL0
+#CHECK:  mrs x0, AMEVCNTR02_EL0
+#CHECK:  mrs x0, AMEVCNTR03_EL0
+#CHECK:  mrs x0, AMEVTYPER00_EL0
+#CHECK:  mrs x0, AMEVTYPER01_EL0
+#CHECK:  mrs x0, AMEVTYPER02_EL0
+#CHECK:  mrs x0, AMEVTYPER03_EL0
+#CHECK:  mrs x0, AMCNTENCLR1_EL0
+#CHECK:  mrs x0, AMCNTENSET1_EL0
+#CHECK:  mrs x0, AMEVCNTR10_EL0
+#CHECK:  mrs x0, AMEVCNTR11_EL0
+#CHECK:  mrs x0, AMEVCNTR12_EL0
+#CHECK:  mrs x0, AMEVCNTR13_EL0
+#CHECK:  mrs x0, AMEVCNTR14_EL0
+#CHECK:  mrs x0, AMEVCNTR15_EL0
+#CHECK:  mrs x0, AMEVCNTR16_EL0
+#CHECK:  mrs x0, AMEVCNTR17_EL0
+#CHECK:  mrs x0, AMEVCNTR18_EL0
+#CHECK:  mrs x0, AMEVCNTR19_EL0
+#CHECK:  mrs x0, AMEVCNTR110_EL0
+#CHECK:  mrs x0, AMEVCNTR111_EL0
+#CHECK:  mrs x0, AMEVCNTR112_EL0
+#CHECK:  mrs x0, AMEVCNTR113_EL0
+#CHECK:  mrs x0, AMEVCNTR114_EL0
+#CHECK:  mrs x0, AMEVCNTR115_EL0
+#CHECK:  mrs x0, AMEVTYPER10_EL0
+#CHECK:  mrs x0, AMEVTYPER11_EL0
+#CHECK:  mrs x0, AMEVTYPER12_EL0
+#CHECK:  mrs x0, AMEVTYPER13_EL0
+#CHECK:  mrs x0, AMEVTYPER14_EL0
+#CHECK:  mrs x0, AMEVTYPER15_EL0
+#CHECK:  mrs x0, AMEVTYPER16_EL0
+#CHECK:  mrs x0, AMEVTYPER17_EL0
+#CHECK:  mrs x0, AMEVTYPER18_EL0
+#CHECK:  mrs x0, AMEVTYPER19_EL0
+#CHECK:  mrs x0, AMEVTYPER110_EL0
+#CHECK:  mrs x0, AMEVTYPER111_EL0
+#CHECK:  mrs x0, AMEVTYPER112_EL0
+#CHECK:  mrs x0, AMEVTYPER113_EL0
+#CHECK:  mrs x0, AMEVTYPER114_EL0
+#CHECK:  mrs x0, AMEVTYPER115_EL0
+
+#CHECK-NO-V84:  msr S3_3_C13_C2_0, x0
+#CHECK-NO-V84:  msr S3_3_C13_C2_3, x0
+#CHECK-NO-V84:  msr S3_3_C13_C2_4, x0
+#CHECK-NO-V84:  msr S3_3_C13_C2_5, x0
+#CHECK-NO-V84:  msr S3_3_C13_C4_0, x0
+#CHECK-NO-V84:  msr S3_3_C13_C4_1, x0
+#CHECK-NO-V84:  msr S3_3_C13_C4_2, x0
+#CHECK-NO-V84:  msr S3_3_C13_C4_3, x0
+#CHECK-NO-V84:  msr S3_3_C13_C3_0, x0
+#CHECK-NO-V84:  msr S3_3_C13_C3_1, x0
+#CHECK-NO-V84:  msr S3_3_C13_C12_0, x0
+#CHECK-NO-V84:  msr S3_3_C13_C12_1, x0
+#CHECK-NO-V84:  msr S3_3_C13_C12_2, x0
+#CHECK-NO-V84:  msr S3_3_C13_C12_3, x0
+#CHECK-NO-V84:  msr S3_3_C13_C12_4, x0
+#CHECK-NO-V84:  msr S3_3_C13_C12_5, x0
+#CHECK-NO-V84:  msr S3_3_C13_C12_6, x0
+#CHECK-NO-V84:  msr S3_3_C13_C12_7, x0
+#CHECK-NO-V84:  msr S3_3_C13_C13_0, x0
+#CHECK-NO-V84:  msr S3_3_C13_C13_1, x0
+#CHECK-NO-V84:  msr S3_3_C13_C13_2, x0
+#CHECK-NO-V84:  msr S3_3_C13_C13_3, x0
+#CHECK-NO-V84:  msr S3_3_C13_C13_4, x0
+#CHECK-NO-V84:  msr S3_3_C13_C13_5, x0
+#CHECK-NO-V84:  msr S3_3_C13_C13_6, x0
+#CHECK-NO-V84:  msr S3_3_C13_C13_7, x0
+#CHECK-NO-V84:  msr S3_3_C13_C14_0, x0
+#CHECK-NO-V84:  msr S3_3_C13_C14_1, x0
+#CHECK-NO-V84:  msr S3_3_C13_C14_2, x0
+#CHECK-NO-V84:  msr S3_3_C13_C14_3, x0
+#CHECK-NO-V84:  msr S3_3_C13_C14_4, x0
+#CHECK-NO-V84:  msr S3_3_C13_C14_5, x0
+#CHECK-NO-V84:  msr S3_3_C13_C14_6, x0
+#CHECK-NO-V84:  msr S3_3_C13_C14_7, x0
+#CHECK-NO-V84:  msr S3_3_C13_C15_0, x0
+#CHECK-NO-V84:  msr S3_3_C13_C15_1, x0
+#CHECK-NO-V84:  msr S3_3_C13_C15_2, x0
+#CHECK-NO-V84:  msr S3_3_C13_C15_3, x0
+#CHECK-NO-V84:  msr S3_3_C13_C15_4, x0
+#CHECK-NO-V84:  msr S3_3_C13_C15_5, x0
+#CHECK-NO-V84:  msr S3_3_C13_C15_6, x0
+#CHECK-NO-V84:  msr S3_3_C13_C15_7, x0
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C2_0
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C2_1
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C2_2
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C2_3
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C2_4
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C2_5
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C4_0
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C4_1
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C4_2
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C4_3
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C6_0
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C6_1
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C6_2
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C6_3
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C3_0
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C3_1
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C12_0
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C12_1
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C12_2
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C12_3
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C12_4
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C12_5
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C12_6
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C12_7
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C13_0
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C13_1
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C13_2
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C13_3
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C13_4
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C13_5
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C13_6
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C13_7
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C14_0
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C14_1
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C14_2
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C14_3
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C14_4
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C14_5
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C14_6
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C14_7
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C15_0
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C15_1
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C15_2
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C15_3
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C15_4
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C15_5
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C15_6
+#CHECK-NO-V84:  mrs x0, S3_3_C13_C15_7
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
new file mode 100644
index 00000000000..fb22ab70854
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-dit.txt
@@ -0,0 +1,14 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+[0x5f,0x41,0x03,0xd5]
+[0xa0,0x42,0x1b,0xd5]
+[0xa0,0x42,0x3b,0xd5]
+
+#CHECK:  msr DIT, #1
+#CHECK:  msr DIT, x0
+#CHECK:  mrs x0, DIT
+
+#CHECK-NO-V84:  msr S0_3_C4_C1_2, xzr
+#CHECK-NO-V84:  msr S3_3_C4_C2_5, x0
+#CHECK-NO-V84:  mrs x0, S3_3_C4_C2_5
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt
new file mode 100644
index 00000000000..ad22000bb82
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-mpam.txt
@@ -0,0 +1,99 @@
+#RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+#RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s | FileCheck %s --check-prefix=CHECK-NOV84
+
+[0x20,0xa5,0x18,0xd5]
+[0x00,0xa5,0x18,0xd5]
+[0x00,0xa5,0x1c,0xd5]
+[0x00,0xa5,0x1e,0xd5]
+[0x00,0xa5,0x1d,0xd5]
+[0x00,0xa4,0x1c,0xd5]
+[0x20,0xa4,0x1c,0xd5]
+[0x00,0xa6,0x1c,0xd5]
+[0x20,0xa6,0x1c,0xd5]
+[0x40,0xa6,0x1c,0xd5]
+[0x60,0xa6,0x1c,0xd5]
+[0x80,0xa6,0x1c,0xd5]
+[0xa0,0xa6,0x1c,0xd5]
+[0xc0,0xa6,0x1c,0xd5]
+[0xe0,0xa6,0x1c,0xd5]
+[0x20,0xa5,0x38,0xd5]
+[0x00,0xa5,0x38,0xd5]
+[0x00,0xa5,0x3c,0xd5]
+[0x00,0xa5,0x3e,0xd5]
+[0x00,0xa5,0x3d,0xd5]
+[0x00,0xa4,0x3c,0xd5]
+[0x20,0xa4,0x3c,0xd5]
+[0x00,0xa6,0x3c,0xd5]
+[0x20,0xa6,0x3c,0xd5]
+[0x40,0xa6,0x3c,0xd5]
+[0x60,0xa6,0x3c,0xd5]
+[0x80,0xa6,0x3c,0xd5]
+[0xa0,0xa6,0x3c,0xd5]
+[0xc0,0xa6,0x3c,0xd5]
+[0xe0,0xa6,0x3c,0xd5]
+[0x80,0xa4,0x38,0xd5]
+
+#CHECK:  msr MPAM0_EL1, x0
+#CHECK:  msr MPAM1_EL1, x0
+#CHECK:  msr MPAM2_EL2, x0
+#CHECK:  msr MPAM3_EL3, x0
+#CHECK:  msr MPAM1_EL12, x0
+#CHECK:  msr MPAMHCR_EL2, x0
+#CHECK:  msr MPAMVPMV_EL2, x0
+#CHECK:  msr MPAMVPM0_EL2, x0
+#CHECK:  msr MPAMVPM1_EL2, x0
+#CHECK:  msr MPAMVPM2_EL2, x0
+#CHECK:  msr MPAMVPM3_EL2, x0
+#CHECK:  msr MPAMVPM4_EL2, x0
+#CHECK:  msr MPAMVPM5_EL2, x0
+#CHECK:  msr MPAMVPM6_EL2, x0
+#CHECK:  msr MPAMVPM7_EL2, x0
+#CHECK:  mrs x0, MPAM0_EL1
+#CHECK:  mrs x0, MPAM1_EL1
+#CHECK:  mrs x0, MPAM2_EL2
+#CHECK:  mrs x0, MPAM3_EL3
+#CHECK:  mrs x0, MPAM1_EL12
+#CHECK:  mrs x0, MPAMHCR_EL2
+#CHECK:  mrs x0, MPAMVPMV_EL2
+#CHECK:  mrs x0, MPAMVPM0_EL2
+#CHECK:  mrs x0, MPAMVPM1_EL2
+#CHECK:  mrs x0, MPAMVPM2_EL2
+#CHECK:  mrs x0, MPAMVPM3_EL2
+#CHECK:  mrs x0, MPAMVPM4_EL2
+#CHECK:  mrs x0, MPAMVPM5_EL2
+#CHECK:  mrs x0, MPAMVPM6_EL2
+#CHECK:  mrs x0, MPAMVPM7_EL2
+#CHECK:  mrs x0, MPAMIDR_EL1
+
+#CHECK-NOV84:  msr S3_0_C10_C5_1, x0
+#CHECK-NOV84:  msr S3_0_C10_C5_0, x0
+#CHECK-NOV84:  msr S3_4_C10_C5_0, x0
+#CHECK-NOV84:  msr S3_6_C10_C5_0, x0
+#CHECK-NOV84:  msr S3_5_C10_C5_0, x0
+#CHECK-NOV84:  msr S3_4_C10_C4_0, x0
+#CHECK-NOV84:  msr S3_4_C10_C4_1, x0
+#CHECK-NOV84:  msr S3_4_C10_C6_0, x0
+#CHECK-NOV84:  msr S3_4_C10_C6_1, x0
+#CHECK-NOV84:  msr S3_4_C10_C6_2, x0
+#CHECK-NOV84:  msr S3_4_C10_C6_3, x0
+#CHECK-NOV84:  msr S3_4_C10_C6_4, x0
+#CHECK-NOV84:  msr S3_4_C10_C6_5, x0
+#CHECK-NOV84:  msr S3_4_C10_C6_6, x0
+#CHECK-NOV84:  msr S3_4_C10_C6_7, x0
+#CHECK-NOV84:  mrs x0, S3_0_C10_C5_1
+#CHECK-NOV84:  mrs x0, S3_0_C10_C5_0
+#CHECK-NOV84:  mrs x0, S3_4_C10_C5_0
+#CHECK-NOV84:  mrs x0, S3_6_C10_C5_0
+#CHECK-NOV84:  mrs x0, S3_5_C10_C5_0
+#CHECK-NOV84:  mrs x0, S3_4_C10_C4_0
+#CHECK-NOV84:  mrs x0, S3_4_C10_C4_1
+#CHECK-NOV84:  mrs x0, S3_4_C10_C6_0
+#CHECK-NOV84:  mrs x0, S3_4_C10_C6_1
+#CHECK-NOV84:  mrs x0, S3_4_C10_C6_2
+#CHECK-NOV84:  mrs x0, S3_4_C10_C6_3
+#CHECK-NOV84:  mrs x0, S3_4_C10_C6_4
+#CHECK-NOV84:  mrs x0, S3_4_C10_C6_5
+#CHECK-NOV84:  mrs x0, S3_4_C10_C6_6
+#CHECK-NOV84:  mrs x0, S3_4_C10_C6_7
+#CHECK-NOV84:  mrs x0, S3_0_C10_C4_4
+
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt
new file mode 100644
index 00000000000..ef38b71fb9e
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+
+0xa0,0x54,0x18,0xd5
+0xa0,0x54,0x38,0xd5
+0xc0,0x54,0x18,0xd5
+0xc0,0x54,0x38,0xd5
+0xe0,0x55,0x18,0xd5
+0xe0,0x55,0x38,0xd5
+0x80,0x54,0x38,0xd5
+
+0x40,0x55,0x18,0xd5
+0x40,0x55,0x38,0xd5
+0x60,0x55,0x18,0xd5
+0x60,0x55,0x38,0xd5
+
+#CHECK:  msr ERXPFGCTL_EL1, x0
+#CHECK:  mrs x0, ERXPFGCTL_EL1
+#CHECK:  msr ERXPFGCDN_EL1, x0
+#CHECK:  mrs x0, ERXPFGCDN_EL1
+#CHECK:  msr ERXTS_EL1, x0
+#CHECK:  mrs x0, ERXTS_EL1
+#CHECK:  mrs x0, ERXPFGF_EL1
+
+#CHECK:  msr ERXMISC2_EL1, x0
+#CHECK:  mrs x0, ERXMISC2_EL1
+#CHECK:  msr ERXMISC3_EL1, x0
+#CHECK:  mrs x0, ERXMISC3_EL1
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-trace.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-trace.txt
new file mode 100644
index 00000000000..d51157e08f9
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-trace.txt
@@ -0,0 +1,23 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+[0x20,0x12,0x18,0xd5]
+[0x20,0x12,0x1c,0xd5]
+[0x20,0x12,0x1d,0xd5]
+[0x20,0x12,0x38,0xd5]
+[0x20,0x12,0x3c,0xd5]
+[0x20,0x12,0x3d,0xd5]
+
+#CHECK:  msr TRFCR_EL1, x0
+#CHECK:  msr TRFCR_EL2, x0
+#CHECK:  msr TRFCR_EL12, x0
+#CHECK:  mrs x0, TRFCR_EL1
+#CHECK:  mrs x0, TRFCR_EL2
+#CHECK:  mrs x0, TRFCR_EL12
+
+#CHECK-NO-V84:  msr S3_0_C1_C2_1, x0
+#CHECK-NO-V84:  msr S3_4_C1_C2_1, x0
+#CHECK-NO-V84:  msr S3_5_C1_C2_1, x0
+#CHECK-NO-V84:  mrs x0, S3_0_C1_C2_1
+#CHECK-NO-V84:  mrs x0, S3_4_C1_C2_1
+#CHECK-NO-V84:  mrs x0, S3_5_C1_C2_1
diff --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-vncr.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-vncr.txt
new file mode 100644
index 00000000000..cfbac5174f4
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-vncr.txt
@@ -0,0 +1,11 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
+
+[0x00,0x22,0x3c,0xd5]
+[0x00,0x22,0x1c,0xd5]
+
+# CHECK:  mrs x0, VNCR_EL2
+# CHECK:  msr VNCR_EL2, x0
+
+# CHECK-NO-V84:  mrs x0, S3_4_C2_C2_0
+# CHECK-NO-V84:  msr S3_4_C2_C2_0, x0