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* [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard ↵Alex Bradbury2019-03-301-5/+15
| | | | | | | | | | | | | | | | | | | | float") ABIs This patch adds support for the RISC-V hard float ABIs, building on top of rL355771, which added basic target-abi parsing and MC layer support. It also builds on some re-organisations and expansion of the upstream ABI and calling convention tests which were recently committed directly upstream. A number of aspects of the RISC-V float hard float ABIs require frontend support (e.g. flattening of structs and passing int+fp for fp+fp structs in a pair of registers), and will be addressed in a Clang patch. As can be seen from the tests, it would be worthwhile extending RISCVMergeBaseOffsets to handle constant pool as well as global accesses. Differential Revision: https://reviews.llvm.org/D59357 llvm-svn: 357352
* [RISCV] Add RV64 CHECK lines to test/CodeGen/RISCV/vararg.ll and prepare for ↵Alex Bradbury2019-03-301-644/+1555
| | | | | | | | | | | | hard float tests vararg.ll previously missed RV64 tests. This patch also prepares for using vararg.ll to test handling of varargs for the ilp32f/ilp32d/lp64f/lp64d hard float ABIs. In these ABIs, varargs are passed as in either the ilp32 or lp64 ABI. Due to some slight codegen differences, different check lines are needed for when RV32D is enabled. llvm-svn: 357350
* [RISCV][NFC] Remove floating point operations from test/CodeGen/RISCV/vararg.llAlex Bradbury2019-03-301-65/+65
| | | | | | | | This minimises differences in output when compiling with hardware floating point support, which will be done in a future patch (to demonstrate the same vararg calling convention is used). llvm-svn: 357339
* [RISCV] Only mark fp as reserved if the function has a dedicated frame pointerAlex Bradbury2019-03-131-4/+4
| | | | | | | | This follows similar logic in the ARM and Mips backends, and allows the free use of s0 in functions without a dedicated frame pointer. The changes in callee-saved-gprs.ll most clearly show the effect of this patch. llvm-svn: 356063
* Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUIAna Pazos2019-01-251-10/+10
| | | | | | This reapplies commit r352010 with RISC-V test fixes. llvm-svn: 352237
* Replace "no-frame-pointer-*" function attributes with "frame-pointer"Francis Visoiu Mistrih2019-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of the effort to refactoring frame pointer code generation. We used to use two function attributes "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" to represent three kinds of frame pointer usage: (all) frames use frame pointer, (non-leaf) frames use frame pointer, (none) frame use frame pointer. This CL makes the idea explicit by using only one enum function attribute "frame-pointer" Option "-frame-pointer=" replaces "-disable-fp-elim" for tools such as llc. "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" are still supported for easy migration to "frame-pointer". tests are mostly updated with // replace command line args ‘-disable-fp-elim=false’ with ‘-frame-pointer=none’ grep -iIrnl '\-disable-fp-elim=false' * | xargs sed -i '' -e "s/-disable-fp-elim=false/-frame-pointer=none/g" // replace command line args ‘-disable-fp-elim’ with ‘-frame-pointer=all’ grep -iIrnl '\-disable-fp-elim' * | xargs sed -i '' -e "s/-disable-fp-elim/-frame-pointer=all/g" Patch by Yuanfang Chen (tabloid.adroit)! Differential Revision: https://reviews.llvm.org/D56351 llvm-svn: 351049
* [RISCV] Re-generate test/CodeGen/RISCV/vararg.ll after r344142Alex Bradbury2018-10-111-34/+32
| | | | | | The improved load-store forwarding committed in r344142 broke this test. llvm-svn: 344238
* [RISCV] Regenerate several tests now enableMultipleCopyHints is enabled by ↵Alex Bradbury2018-10-051-38/+38
| | | | | | | | default r343851 caused codegen changes in several tests. This patch regenerates them. llvm-svn: 343873
* [RISCV][NFC] Remove dead CHECK lines from vararg.ll testAlex Bradbury2018-10-041-310/+0
| | | | | | The RISCV32 check prefix is no longer used so these lines are dead. llvm-svn: 343757
* [RISCV] Expand function call to "call" pseudoinstructionShiva Chen2018-04-251-48/+16
| | | | | | | | | | | | | | | | To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
* [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bitsAlex Bradbury2018-04-181-16/+8
| | | | | | | These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-181-12/+20
| | | | | | | | | Reverts rL330224, while issues with the C extension and missed common subexpression elimination opportunities are addressed. Neither of these issues are visible in current RISC-V backend unit tests, which clearly need expanding. llvm-svn: 330281
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-171-20/+12
| | | | | | | | | | | | | | The implementation follows the MIPS backend and expands the pseudo instruction directly during asm parsing. As the result, only real MC instructions are emitted to the MCStreamer. Additionally, PseudoLI instructions are emitted during codegen. The actual expansion to real instructions is performed during MI to MC lowering and is similar to the expansion performed by the GNU Assembler. Differential Revision: https://reviews.llvm.org/D41949 Patch by Mario Werner. llvm-svn: 330224
* [RISCV] Implement frame pointer eliminationAlex Bradbury2018-01-181-162/+798
| | | | llvm-svn: 322839
* [RISCV] Support for varargsAlex Bradbury2018-01-101-0/+535
Includes support for expanding va_copy. Also adds support for using 'aligned' registers when necessary for vararg calls, and ensure the frame pointer always points to the bottom of the vararg spill region. This is necessary to ensure that the saved return address and stack pointer are always available at fixed known offsets of the frame pointer. Differential Revision: https://reviews.llvm.org/D40805 llvm-svn: 322215
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