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| author | Alex Bradbury <asb@lowrisc.org> | 2018-04-18 20:34:23 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-04-18 20:34:23 +0000 |
| commit | 3ff2022bb940237f10584d81da8d21bd62e76c7d (patch) | |
| tree | 41284359b11859abf59ef75e2a3b238a7da3362b /llvm/test/CodeGen/RISCV/vararg.ll | |
| parent | f4a3ff008d58fca4031f03644d96a634cd9815ba (diff) | |
| download | bcm5719-llvm-3ff2022bb940237f10584d81da8d21bd62e76c7d.tar.gz bcm5719-llvm-3ff2022bb940237f10584d81da8d21bd62e76c7d.zip | |
[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits
These immediates can be materialised with just an lui, rather than an lui+addi
pair.
llvm-svn: 330293
Diffstat (limited to 'llvm/test/CodeGen/RISCV/vararg.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/vararg.ll | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll index 61a6178e095..c930f7d1af6 100644 --- a/llvm/test/CodeGen/RISCV/vararg.ll +++ b/llvm/test/CodeGen/RISCV/vararg.ll @@ -264,10 +264,9 @@ define void @va1_caller() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, 261888 -; RV32I-FPELIM-NEXT: mv a3, a0 ; RV32I-FPELIM-NEXT: lui a0, %hi(va1) ; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va1) +; RV32I-FPELIM-NEXT: lui a3, 261888 ; RV32I-FPELIM-NEXT: addi a4, zero, 2 ; RV32I-FPELIM-NEXT: mv a2, zero ; RV32I-FPELIM-NEXT: jalr a0 @@ -281,10 +280,9 @@ define void @va1_caller() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, 261888 -; RV32I-WITHFP-NEXT: mv a3, a0 ; RV32I-WITHFP-NEXT: lui a0, %hi(va1) ; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va1) +; RV32I-WITHFP-NEXT: lui a3, 261888 ; RV32I-WITHFP-NEXT: addi a4, zero, 2 ; RV32I-WITHFP-NEXT: mv a2, zero ; RV32I-WITHFP-NEXT: jalr a0 @@ -472,10 +470,9 @@ define void @va2_caller() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, 261888 -; RV32I-FPELIM-NEXT: mv a3, a0 ; RV32I-FPELIM-NEXT: lui a0, %hi(va2) ; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va2) +; RV32I-FPELIM-NEXT: lui a3, 261888 ; RV32I-FPELIM-NEXT: mv a2, zero ; RV32I-FPELIM-NEXT: jalr a0 ; RV32I-FPELIM-NEXT: lw ra, 12(sp) @@ -488,10 +485,9 @@ define void @va2_caller() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, 261888 -; RV32I-WITHFP-NEXT: mv a3, a0 ; RV32I-WITHFP-NEXT: lui a0, %hi(va2) ; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va2) +; RV32I-WITHFP-NEXT: lui a3, 261888 ; RV32I-WITHFP-NEXT: mv a2, zero ; RV32I-WITHFP-NEXT: jalr a0 ; RV32I-WITHFP-NEXT: lw s0, 8(sp) @@ -716,13 +712,11 @@ define void @va3_caller() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, 261888 -; RV32I-FPELIM-NEXT: mv a2, a0 -; RV32I-FPELIM-NEXT: lui a0, 262144 -; RV32I-FPELIM-NEXT: mv a5, a0 ; RV32I-FPELIM-NEXT: lui a0, %hi(va3) ; RV32I-FPELIM-NEXT: addi a3, a0, %lo(va3) ; RV32I-FPELIM-NEXT: addi a0, zero, 2 +; RV32I-FPELIM-NEXT: lui a2, 261888 +; RV32I-FPELIM-NEXT: lui a5, 262144 ; RV32I-FPELIM-NEXT: mv a1, zero ; RV32I-FPELIM-NEXT: mv a4, zero ; RV32I-FPELIM-NEXT: jalr a3 @@ -736,13 +730,11 @@ define void @va3_caller() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, 261888 -; RV32I-WITHFP-NEXT: mv a2, a0 -; RV32I-WITHFP-NEXT: lui a0, 262144 -; RV32I-WITHFP-NEXT: mv a5, a0 ; RV32I-WITHFP-NEXT: lui a0, %hi(va3) ; RV32I-WITHFP-NEXT: addi a3, a0, %lo(va3) ; RV32I-WITHFP-NEXT: addi a0, zero, 2 +; RV32I-WITHFP-NEXT: lui a2, 261888 +; RV32I-WITHFP-NEXT: lui a5, 262144 ; RV32I-WITHFP-NEXT: mv a1, zero ; RV32I-WITHFP-NEXT: mv a4, zero ; RV32I-WITHFP-NEXT: jalr a3 |
