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| author | Alex Bradbury <asb@lowrisc.org> | 2019-03-30 17:59:30 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2019-03-30 17:59:30 +0000 |
| commit | 0b2803ee6578b50a536bfbacfba288cefa0172c6 (patch) | |
| tree | 7520c7c2fdc6912d4f426ae47b8cbf8801653205 /llvm/test/CodeGen/RISCV/vararg.ll | |
| parent | 10c9032c02394c6dd6102f4387cd315f19738616 (diff) | |
| download | bcm5719-llvm-0b2803ee6578b50a536bfbacfba288cefa0172c6.tar.gz bcm5719-llvm-0b2803ee6578b50a536bfbacfba288cefa0172c6.zip | |
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs
This patch adds support for the RISC-V hard float ABIs, building on top of
rL355771, which added basic target-abi parsing and MC layer support. It also
builds on some re-organisations and expansion of the upstream ABI and calling
convention tests which were recently committed directly upstream.
A number of aspects of the RISC-V float hard float ABIs require frontend
support (e.g. flattening of structs and passing int+fp for fp+fp structs in a
pair of registers), and will be addressed in a Clang patch.
As can be seen from the tests, it would be worthwhile extending
RISCVMergeBaseOffsets to handle constant pool as well as global accesses.
Differential Revision: https://reviews.llvm.org/D59357
llvm-svn: 357352
Diffstat (limited to 'llvm/test/CodeGen/RISCV/vararg.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/vararg.ll | 20 |
1 files changed, 15 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll index 5486314af1d..34132825c2a 100644 --- a/llvm/test/CodeGen/RISCV/vararg.ll +++ b/llvm/test/CodeGen/RISCV/vararg.ll @@ -5,16 +5,26 @@ ; RUN: | FileCheck -check-prefix=ILP32-ILP32F-WITHFP %s ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s +; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32f \ +; RUN: -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s +; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \ +; RUN: -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV32D-ILP32-ILP32F-ILP32D-FPELIM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s +; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64f \ +; RUN: -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s +; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d \ +; RUN: -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-FPELIM %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs -frame-pointer=all < %s \ ; RUN: | FileCheck -check-prefix=LP64-LP64F-LP64D-WITHFP %s -; TODO: RUN lines for ilp32f/ilp32d/lp64f/lp64d must be added when hard float -; ABI Support lands. The same vararg calling convention is used for -; ilp32/ilp32f/ilp32d and for lp64/lp64f/lp64d. Different CHECK lines are -; required for RV32D due to slight codegen differences due to the way the -; f64 load operations are lowered. +; The same vararg calling convention is used for ilp32/ilp32f/ilp32d and for +; lp64/lp64f/lp64d. Different CHECK lines are required for RV32D due to slight +; codegen differences due to the way the f64 load operations are lowered. declare void @llvm.va_start(i8*) declare void @llvm.va_end(i8*) |
