[RISCV] Regenerate several tests now enableMultipleCopyHints is enabled by default

r343851 caused codegen changes in several tests. This patch regenerates them.

llvm-svn: 343873

1 files changed, 38 insertions, 38 deletions

diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
index 486d49bb0f0..ac08f346fbb 100644
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -367,21 +367,21 @@ define double @va3(i32 %a, double %b, ...) nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -32
 ; RV32I-FPELIM-NEXT:    sw ra, 4(sp)
+; RV32I-FPELIM-NEXT:    mv t0, a2
+; RV32I-FPELIM-NEXT:    mv a0, a1
 ; RV32I-FPELIM-NEXT:    sw a7, 28(sp)
 ; RV32I-FPELIM-NEXT:    sw a6, 24(sp)
 ; RV32I-FPELIM-NEXT:    sw a5, 20(sp)
 ; RV32I-FPELIM-NEXT:    sw a4, 16(sp)
 ; RV32I-FPELIM-NEXT:    sw a3, 12(sp)
-; RV32I-FPELIM-NEXT:    addi a0, sp, 27
-; RV32I-FPELIM-NEXT:    sw a0, 0(sp)
-; RV32I-FPELIM-NEXT:    addi a0, sp, 19
-; RV32I-FPELIM-NEXT:    andi a0, a0, -8
-; RV32I-FPELIM-NEXT:    lw a4, 0(a0)
-; RV32I-FPELIM-NEXT:    ori a0, a0, 4
-; RV32I-FPELIM-NEXT:    lw a3, 0(a0)
-; RV32I-FPELIM-NEXT:    mv a0, a1
-; RV32I-FPELIM-NEXT:    mv a1, a2
-; RV32I-FPELIM-NEXT:    mv a2, a4
+; RV32I-FPELIM-NEXT:    addi a1, sp, 27
+; RV32I-FPELIM-NEXT:    sw a1, 0(sp)
+; RV32I-FPELIM-NEXT:    addi a1, sp, 19
+; RV32I-FPELIM-NEXT:    andi a1, a1, -8
+; RV32I-FPELIM-NEXT:    lw a2, 0(a1)
+; RV32I-FPELIM-NEXT:    ori a1, a1, 4
+; RV32I-FPELIM-NEXT:    lw a3, 0(a1)
+; RV32I-FPELIM-NEXT:    mv a1, t0
 ; RV32I-FPELIM-NEXT:    call __adddf3
 ; RV32I-FPELIM-NEXT:    lw ra, 4(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 32
@@ -393,21 +393,21 @@ define double @va3(i32 %a, double %b, ...) nounwind {
 ; RV32I-WITHFP-NEXT:    sw ra, 20(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 16(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 24
+; RV32I-WITHFP-NEXT:    mv t0, a2
+; RV32I-WITHFP-NEXT:    mv a0, a1
 ; RV32I-WITHFP-NEXT:    sw a7, 20(s0)
 ; RV32I-WITHFP-NEXT:    sw a6, 16(s0)
 ; RV32I-WITHFP-NEXT:    sw a5, 12(s0)
 ; RV32I-WITHFP-NEXT:    sw a4, 8(s0)
 ; RV32I-WITHFP-NEXT:    sw a3, 4(s0)
-; RV32I-WITHFP-NEXT:    addi a0, s0, 19
-; RV32I-WITHFP-NEXT:    sw a0, -12(s0)
-; RV32I-WITHFP-NEXT:    addi a0, s0, 11
-; RV32I-WITHFP-NEXT:    andi a0, a0, -8
-; RV32I-WITHFP-NEXT:    lw a4, 0(a0)
-; RV32I-WITHFP-NEXT:    ori a0, a0, 4
-; RV32I-WITHFP-NEXT:    lw a3, 0(a0)
-; RV32I-WITHFP-NEXT:    mv a0, a1
-; RV32I-WITHFP-NEXT:    mv a1, a2
-; RV32I-WITHFP-NEXT:    mv a2, a4
+; RV32I-WITHFP-NEXT:    addi a1, s0, 19
+; RV32I-WITHFP-NEXT:    sw a1, -12(s0)
+; RV32I-WITHFP-NEXT:    addi a1, s0, 11
+; RV32I-WITHFP-NEXT:    andi a1, a1, -8
+; RV32I-WITHFP-NEXT:    lw a2, 0(a1)
+; RV32I-WITHFP-NEXT:    ori a1, a1, 4
+; RV32I-WITHFP-NEXT:    lw a3, 0(a1)
+; RV32I-WITHFP-NEXT:    mv a1, t0
 ; RV32I-WITHFP-NEXT:    call __adddf3
 ; RV32I-WITHFP-NEXT:    lw s0, 16(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 20(sp)
@@ -435,22 +435,22 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    addi sp, sp, -32
 ; RV32I-FPELIM-NEXT:    sw ra, 4(sp)
+; RV32I-FPELIM-NEXT:    mv t0, a2
+; RV32I-FPELIM-NEXT:    mv a0, a1
 ; RV32I-FPELIM-NEXT:    sw a7, 28(sp)
 ; RV32I-FPELIM-NEXT:    sw a6, 24(sp)
 ; RV32I-FPELIM-NEXT:    sw a5, 20(sp)
 ; RV32I-FPELIM-NEXT:    sw a4, 16(sp)
 ; RV32I-FPELIM-NEXT:    sw a3, 12(sp)
-; RV32I-FPELIM-NEXT:    addi a0, sp, 19
-; RV32I-FPELIM-NEXT:    andi a0, a0, -8
-; RV32I-FPELIM-NEXT:    ori a3, a0, 4
+; RV32I-FPELIM-NEXT:    addi a1, sp, 19
+; RV32I-FPELIM-NEXT:    andi a1, a1, -8
+; RV32I-FPELIM-NEXT:    ori a3, a1, 4
 ; RV32I-FPELIM-NEXT:    sw a3, 0(sp)
-; RV32I-FPELIM-NEXT:    lw a4, 0(a0)
-; RV32I-FPELIM-NEXT:    addi a0, a3, 4
-; RV32I-FPELIM-NEXT:    sw a0, 0(sp)
+; RV32I-FPELIM-NEXT:    lw a2, 0(a1)
+; RV32I-FPELIM-NEXT:    addi a1, a3, 4
+; RV32I-FPELIM-NEXT:    sw a1, 0(sp)
 ; RV32I-FPELIM-NEXT:    lw a3, 0(a3)
-; RV32I-FPELIM-NEXT:    mv a0, a1
-; RV32I-FPELIM-NEXT:    mv a1, a2
-; RV32I-FPELIM-NEXT:    mv a2, a4
+; RV32I-FPELIM-NEXT:    mv a1, t0
 ; RV32I-FPELIM-NEXT:    call __adddf3
 ; RV32I-FPELIM-NEXT:    lw ra, 4(sp)
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 32
@@ -462,22 +462,22 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind {
 ; RV32I-WITHFP-NEXT:    sw ra, 20(sp)
 ; RV32I-WITHFP-NEXT:    sw s0, 16(sp)
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 24
+; RV32I-WITHFP-NEXT:    mv t0, a2
+; RV32I-WITHFP-NEXT:    mv a0, a1
 ; RV32I-WITHFP-NEXT:    sw a7, 20(s0)
 ; RV32I-WITHFP-NEXT:    sw a6, 16(s0)
 ; RV32I-WITHFP-NEXT:    sw a5, 12(s0)
 ; RV32I-WITHFP-NEXT:    sw a4, 8(s0)
 ; RV32I-WITHFP-NEXT:    sw a3, 4(s0)
-; RV32I-WITHFP-NEXT:    addi a0, s0, 11
-; RV32I-WITHFP-NEXT:    andi a0, a0, -8
-; RV32I-WITHFP-NEXT:    ori a3, a0, 4
+; RV32I-WITHFP-NEXT:    addi a1, s0, 11
+; RV32I-WITHFP-NEXT:    andi a1, a1, -8
+; RV32I-WITHFP-NEXT:    ori a3, a1, 4
 ; RV32I-WITHFP-NEXT:    sw a3, -12(s0)
-; RV32I-WITHFP-NEXT:    lw a4, 0(a0)
-; RV32I-WITHFP-NEXT:    addi a0, a3, 4
-; RV32I-WITHFP-NEXT:    sw a0, -12(s0)
+; RV32I-WITHFP-NEXT:    lw a2, 0(a1)
+; RV32I-WITHFP-NEXT:    addi a1, a3, 4
+; RV32I-WITHFP-NEXT:    sw a1, -12(s0)
 ; RV32I-WITHFP-NEXT:    lw a3, 0(a3)
-; RV32I-WITHFP-NEXT:    mv a0, a1
-; RV32I-WITHFP-NEXT:    mv a1, a2
-; RV32I-WITHFP-NEXT:    mv a2, a4
+; RV32I-WITHFP-NEXT:    mv a1, t0
 ; RV32I-WITHFP-NEXT:    call __adddf3
 ; RV32I-WITHFP-NEXT:    lw s0, 16(sp)
 ; RV32I-WITHFP-NEXT:    lw ra, 20(sp)