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* [DAGCombine] Check the uses of negated floating constant and remove the hackQingShan Zhang2020-06-261-0/+101
| | | | | | | | | | | | | PowerPC hits an assertion due to somewhat the same reason as https://reviews.llvm.org/D70975. Though there are already some hack, it still failed with some case, when the operand 0 is NOT a const fp, it is another fma that with const fp. And that const fp is negated which result in multi-uses. A better fix is to check the uses of the negated const fp. If there are already use of its negated value, we will have benefit as no extra Node is added. Differential revision: https://reviews.llvm.org/D75501 (cherry picked from commit 3906ae387f0775dfe4426e4336748269fafbd190)
* [PPCAsmPrinter] support 'L' output template for memory operandsNick Desaulniers2020-06-251-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: L is meant to support the second word used by 32b calling conventions for 64b arguments. This is required for build 32b PowerPC Linux kernels after upstream commit 334710b1496a ("powerpc/uaccess: Implement unsafe_put_user() using 'asm goto'") Thanks for the report from @nathanchance, and reference to GCC's implementation from @segher. Fixes: pr/46186 Fixes: https://github.com/ClangBuiltLinux/linux/issues/1044 Reviewers: echristo, hfinkel, MaskRay Reviewed By: MaskRay Subscribers: MaskRay, wuzish, nemanjai, hiraditya, kbarton, steven.zhang, llvm-commits, segher, nathanchance, srhines Tags: #llvm Differential Revision: https://reviews.llvm.org/D81767 (cherry picked from commit 2d8e105db6bea10a6b96e4a094e73a87987ef909)
* [PowerPC] Do not assume operand of ADDI is an immediateNemanja Ivanovic2020-06-231-0/+52
| | | | | | | | | | After pseudo-expansion, we may end up with ADDI (add immediate) instructions where the operand is not an immediate but a relocation. For such instructions, attempts to get the immediate result in assertion failures for obvious reasons. Fixes: https://bugs.llvm.org/show_bug.cgi?id=45432 (cherry picked from commit a56d057dfe3127c111c3470606c04e96d35b1fa3)
* [PowerPC] Unaligned FP default should apply to scalars onlyNemanja Ivanovic2020-06-231-0/+132
| | | | | | | | | | As reported in PR45186, we could be in a situation where we don't want to handle unaligned memory accesses for FP scalars but still have VSX (which allows unaligned access for vectors). Change the default to only apply to scalars. Fixes: https://bugs.llvm.org/show_bug.cgi?id=45186 (cherry picked from commit 099a875f28d0131a6ae85af91b9eb8627917fbbe)
* [PowerPC] Prevent legalization loop from promoting SELECT_CC from v4i32 to v4i32Nemanja Ivanovic2020-06-221-0/+58
| | | | | | | | | | | | | As reported in https://bugs.llvm.org/show_bug.cgi?id=45709 we can hit an infinite loop in legalization since we set the legalization action for ISD::SELECT_CC for all fixed length vector types to Promote. Without some different legalization action for the type being promoted to, the legalizer simply loops. Since we don't have patterns to match the node, the right legalization action should be Expand. Differential revision: https://reviews.llvm.org/D79854 (cherry picked from commit 793cc518b9428a0b7a40c59d4ecd5939a7bc84f7)
* [PowerPC] Add missing handling for half precisionTom Stellard2020-06-222-176/+54
| | | | | | | | | | | | The fix for PR39865 took care of some of the handling for half precision but it missed a number of issues that still exist. This patch fixes the remaining issues that cause crashes in the PPC back end. Fixes: https://bugs.llvm.org/show_bug.cgi?id=45776 Differential revision: https://reviews.llvm.org/D79283 (cherry picked from commit 1a493b0fa556a07c728862c3c3f70bfd8683bef0)
* [PowerPC] Do not attempt to reuse load for 64-bit FP_TO_UINT without FPCVTNemanja Ivanovic2020-05-191-0/+59
| | | | | | | | | | | | We call the function that attempts to reuse the conversion without checking whether the target matches the constraints that the callee expects. This patch adds the check prior to the call. Fixes: https://bugs.llvm.org/show_bug.cgi?id=43976 Differential revision: https://reviews.llvm.org/D77564 (cherry picked from commit 64b31d96dfd6c05e6d52d8798726dec60502cfde)
* [PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabledKai Luo2020-04-221-2/+11
| | | | | | | | | | | | | Summary: In https://bugs.llvm.org/show_bug.cgi?id=45297, it fails selecting instructions for `PPCISD::ST_VSR_SCAL_INT`. The reason it generate the `PPCISD::ST_VSR_SCAL_INT` with `-power8-vector` in IR is PPC's combiner checks `hasP8Altivec` rather than `hasP8Vector`. This patch should resolve PR45297. Differential Revision: https://reviews.llvm.org/D76773 (cherry picked from commit 8eb40e41f6ec99985a292e342ec303a0bd6f5f41)
* [PowerPC] Fix test for PR45297 to adapt build without asserts. NFC.Kai Luo2020-04-221-1/+1
| | | | (cherry picked from commit 26b46b67d806a5299a93b1b3bca1548cb47487ff)
* [PowerPC] Enhance test for PR45297. NFC.Kai Luo2020-04-221-4/+7
| | | | (cherry picked from commit 351b19231554d4dba29c42c798176f1ff3286a32)
* [PowerPC] Pre-commit reduced test case for PR45297. NFC.Kai Luo2020-04-221-0/+10
| | | | (cherry picked from commit 70f9f4dd9d19ed2cec0d9adf60fede9401898b85)
* [PowerPC] Update alignment for ReuseLoadInfo in LowerFP_TO_INTForReuseKai Luo2020-04-161-0/+44
| | | | | | | | | | | | | In LowerFP_TO_INTForReuse, when emitting `stfiwx`, alignment of 4 is set for the `MachineMemOperand`, but RLI(ReuseLoadInfo)'s alignment is not updated for following loads. It's related to failed alignment check reported in https://bugs.llvm.org/show_bug.cgi?id=45297 Differential Revision: https://reviews.llvm.org/D77624 Backport b7d5229d789b7cb2747226d528ed016624b11cea.
* [DAGCombine] Fix splitting indexed loads in ForwardStoreValueToDirectLoad()Nemanja Ivanovic2020-04-141-0/+58
| | | | | | | | | | | | | | | In DAGCombiner::visitLOAD() we perform some checks before breaking up an indexed load. However, we don't do the same checking in ForwardStoreValueToDirectLoad() which can lead to failures later during combining (see: https://bugs.llvm.org/show_bug.cgi?id=45301). This patch just adds the same checks to this function as well. Fixes: https://bugs.llvm.org/show_bug.cgi?id=45301 Differential revision: https://reviews.llvm.org/D76778 (cherry picked from commit 482141134729237072cb94248381dab96ce34374)
* [Codegen] Revert rL354676/rL354677 and followups - introduced PR43446 miscompileRoman Lebedev2020-02-261-2/+6
| | | | | | | | | | This reverts https://reviews.llvm.org/D58468 (rL354676, 44037d7a6377ec8e5542cced73583283334b516b), and all and any follow-ups to that code block. https://bugs.llvm.org/show_bug.cgi?id=43446 (cherry picked from commit d20907d1de89bf63b589fadd8c096d4895e47fba)
* Revert "[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field"Jeremy Morse2020-02-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | This reverts commit ed29dbaafa49bb8c9039a35f768244c394411fea. I'm backing out D68945, which as the discussion for D73526 shows, doesn't seem to handle the -O0 path through the codegen backend correctly. I'll reland the patch when a fix is worked out, apologies for all the churn. The two parent commits are part of this revert too. Conflicts: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/test/DebugInfo/X86/dbg-addr-dse.ll SelectionDAGBuilder conflict is due to a nearby change in e39e2b4a79c6 that's technically unrelated. dbg-addr-dse.ll conflicted because 41206b61e30c (legitimately) changes the order of two lines. There are further modifications to dbg-value-func-arg.ll: it landed after the patch being reverted, and I've converted indirection to be represented by the isIndirect field rather than DW_OP_deref. (cherry picked from commit 6531a78ac4b5b229bce272706593a0bc873877d7)
* [StackColoring] Remap FixedStackPseudoSourceValue frame index referenced by ↵Fangrui Song2020-01-211-0/+171
| | | | | | | | | | | | | | | | | MachineMemOperand StackColoring::remapInstructions() remaps MachineOperand frame index (e.g. %stack.1 -> %stack.0) but does not remap FixedStackPseudoSourceValue frame index (e.g. store 4 into %stack.1.ap2.i.i) referenced by MachineMemoryOperand. This can cause an assertion failure when LiveDebugValues references a dead stack object. It is difficult to craft a test case. -g, va_copy and stack-coloring are required. I can only reproduce it on ppc32. (cherry picked from commit eaab1bf21e1d6803fd217fe6052537fc33b06837) (cherry picked from commit 854f7be20a0cb1a95671a16d6cc8200107ee25f4) (cherry picked from commit 7a8b0b1595e7dc878b48cf9bbaa652087a6895db)
* [AIX][XCOFF] Supporting the ReadOnlyWithRel SectionKnddiggerlin2020-01-141-0/+19
| | | | | | | | | | SUMMARY: In this patch we put the global variable in a Csect which's SectionKind is "ReadOnlyWithRel" into Data Section. Reviewers: hubert.reinterpretcast,jasonliu,Xiangling_L Subscribers: wuzish, nemanjai, hiraditya Differential Revision: https://reviews.llvm.org/D72461
* [AIX] ExternalSymbolSDNode loweringXiangling Liao2020-01-142-0/+186
| | | | | | | | For memcpy/memset/memmove etc., replace ExternalSymbolSDNode with a MCSymbolSDNode, which have a prefix dot before function name as entry point symbol. Differential Revision: https://reviews.llvm.org/D70718
* [PowerPC] [NFC] set instruction number as 1st priority of lsr cost model.Zheng Chen2020-01-141-0/+66
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* [FPEnv] Fix chain handling for fpexcept.strict nodesUlrich Weigand2020-01-131-9/+9
| | | | | | | | | | | | | | | | | We need to ensure that fpexcept.strict nodes are not optimized away even if the result is unused. To do that, we need to chain them into the block's terminator nodes, like already done for PendingExcepts. This patch adds two new lists of pending chains, PendingConstrainedFP and PendingConstrainedFPStrict to hold constrained FP intrinsic nodes without and with fpexcept.strict markers. This allows not only to solve the above problem, but also to relax chains a bit further by no longer flushing all FP nodes before a store or other memory access. (They are still flushed before nodes with other side effects.) Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D72341
* [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwinFangrui Song2020-01-121-140/+0
| | | | | | | | Darwin support has been removed. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D72063
* [NFC] [PowerPC] Update mi-peephole-splat testQiu Chaofan2020-01-111-23/+115
| | | | | Use script to re-generate the test case, for easier comparison with future patches.
* [AIX] Allow vararg calls when all arguments reside in registersjasonliu2020-01-102-2/+291
| | | | | | | | | | | | | | | | | | | | | | | Summary: This patch pushes the AIX vararg unimplemented error diagnostic later and allows vararg calls so long as all the arguments can be passed in register. This patch extends the AIX calling convention implementation to initialize GPR(s) for vararg float arguments. On AIX, both GPR(s) and FPR are allocated for floating point arguments. The GPR(s) are only initialized for vararg calls, otherwise the callee is expected to retrieve the float argument in the FPR. f64 in AIX PPC32 requires special handling in order to allocated and initialize 2 GPRs. This is performed with bitcast, SRL, truncation to initialize one GPR for the MSW and bitcast, truncations to initialize the other GPR for the LSW. A future patch will follow to add support for arguments passed on the stack. Patch provided by: cebowleratibm Reviewers: sfertile, ZarkoCA, hubert.reinterpretcast Differential Revision: https://reviews.llvm.org/D71013
* [PowerPC] Handle constant zero bits in BitPermutationSelectorNemanja Ivanovic2020-01-101-0/+141
| | | | | | | | | | We currently crash when analyzing an AssertZExt node that has some bits that are constant zeros (i.e. as a result of an and with a constant). This issue was reported in https://bugs.llvm.org/show_bug.cgi?id=41088 and this patch fixes that. Differential revision: https://reviews.llvm.org/D72038
* [DAGCombine] Fold the (fma -x, y, -z) to -(fma x, y, z)QingShan Zhang2020-01-095-37/+28
| | | | | | | This is a positive combination as long as the NEG is NOT free, as we are reducing the number of NEG from two to one. Differential Revision: https://reviews.llvm.org/D72312
* [PowerPC] when folding rlwinm+rlwinm. to andi., we should use first rlwinmZheng Chen2020-01-081-3/+18
| | | | | | | | | | | | | | | | | input reg. %2:gprc = RLWINM %1:gprc, 27, 5, 10 %3:gprc = RLWINM_rec %2:gprc, 8, 5, 10, implicit-def $cr0 ==> %3:gprc = ANDI_rec %1, 0, implicit-def $cr0 we should use %1 instead of %2 as ANDI_rec input. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D71885
* [NFC][Test] Add the option -enable-no-signed-zeros-fp-math for testQingShan Zhang2020-01-081-2/+4
| | | | fma-combine.ll
* [PowerPC][Triple] Use elfv2 on freebsd>=13 and linux-muslFangrui Song2020-01-071-2/+0
| | | | | | | | | | | | | | | | | | | Summary: Every powerpc64le platform uses elfv2. For powerpc64, the environments "elfv1" and "elfv2" were added for FreeBSD ELFv1->ELFv2 migration in D61950. FreeBSD developers have decided to use OS versions to select ABI, and no one is relying on the environments. Also use elfv2 on powerpc64-linux-musl. Users can always use -mabi=elfv1 and -mabi=elfv2 to override the default ABI. Reviewed By: adalava Differential Revision: https://reviews.llvm.org/D72352
* [AIX][XCOFF]Implement mergeable constdiggerlin2020-01-071-0/+166
| | | | | | | | | | SUMMARY: In this patch, we map mergeable const objects to the read-only section in the same manner as const objects that are not mergeable. Reviewers: hubert.reinterpretcast,jasonliu Subscribers: wuzish, nemanjai, hiraditya Differential Revision: https://reviews.llvm.org/D71551
* [NFC][Test] Add a test to verify the DAGCombine of fmaQingShan Zhang2020-01-071-0/+143
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* [PowerPC][NFC] Rename record instructions to use _rec suffix instead of oJinsong Ji2020-01-069-166/+166
| | | | | | | | | | | | | | | | | | | We use o suffix to indicate record form instuctions, (as it is similar to dot '.' in mne?) This was fine before, as we did not support XO-form. However, with https://reviews.llvm.org/D66902, we now have XO-form support. It becomes confusing now to still use 'o' for record form, and it is weird to have something like 'Oo' . This patch rename all 'o' instructions to use '_rec' instead. Also rename `isDot` to `isRecordForm`. Reviewed By: #powerpc, hfinkel, nemanjai, steven.zhang, lkail Differential Revision: https://reviews.llvm.org/D70758
* [AIX] Use csect reference for function address constantsdiggerlin2020-01-061-0/+32
| | | | | | | | | | | | | | | | | SUMMARY: We currently emit a reference for function address constants as labels; for example: foo_ptr: .long foo however, there may be no such label in the case where the function is undefined. Although the label exists when the function is defined, we will (to be consistent) also use a csect reference in that case. Reviewers: daltenty,hubert.reinterpretcast,jasonliu,Xiangling_L Subscribers: cebowleratibm, wuzish, nemanjai Differential Revision: https://reviews.llvm.org/D71144
* [DAGCombine] Don't check the legality of type when combine the SIGN_EXTEND_INREGQingShan Zhang2020-01-061-4/+1
| | | | | | | | | | | | | | | | | | | | | | This is the DAG node for SIGN_EXTEND_INREG : t21: v4i32 = sign_extend_inreg t18, ValueType:ch:v4i16 It has two operands. The first one is the value it want to extend, and the second one is the type to specify how to extend the value. For this example, it means that, it is signed extend the t18(v4i32) from v4i16 to v4i32. That is the semantics of c code: vector int foo(vector int m) { return m << 16 >> 16; } And it could be any vector type that hardware support the operation, though the type 'v4i16' is NOT legal for the target. When we are trying to combine the srl + sra, what we did now is calling the TLI.isOperationLegal(), which will also check the legality of the type. That doesn't make sense. Differential Revision: https://reviews.llvm.org/D70230
* [PowerPC]: Fix predicate handling with SPEJustin Hibbits2020-01-021-202/+510
| | | | | SPE floating-point compare instructions only update the GT bit in the CR field. All predicates must therefore be reduced to GT/LE.
* Run update_llc_test_checks against SPE tests.Justin Hibbits2020-01-021-175/+670
| | | | | This is in preparation for further tests which are better generated with the script. No functional change.
* [PowerPC][AIX] Enable sret arguments.Sean Fertile2020-01-021-7/+90
| | | | | | Removes the fatal error for sret arguments and adds lit testing. Differential Revision: https://reviews.llvm.org/D71504
* [PowerPC] Only legalize FNEARBYINT with unsafe fp mathNemanja Ivanovic2020-01-022-79/+253
| | | | | | | Commit 0f0330a78709 legalized these nodes on PPC without consideration of unsafe math which means that we get inexact exceptions raised for nearbyint. Since this doesn't conform to the standard, switch this legalization to depend on unsafe fp math.
* [NFC] Add comments in unit test aix-xcoff-toc.ll to clarify the intentjasonliu2019-12-311-0/+10
| | | | | Address David's post review comment in https://reviews.llvm.org/D71667. Add comments to clarify what we are testing in that file.
* [PowerPC] Legalize rounding nodesNemanja Ivanovic2019-12-304-278/+665
| | | | | | | | VSX provides a full complement of rounding instructions yet we somehow ended up with some of them legal and others not. This just legalizes all of the FP rounding nodes and the FP -> int rounding nodes with unsafe math. Differential revision: https://reviews.llvm.org/D69949
* [PowerPC] Exploit the rlwinm instructions for "and" with constantQingShan Zhang2019-12-303-8/+5
| | | | | | | | | | | | | | | | | | | | For now, PowerPC will using several instructions to get the constant and "and" it with the following case: define i32 @test1(i32 %a) { %and = and i32 %a, -2 ret i32 %and } However, we could exploit it with the rotate mask instructions. MB ME +----------------------+ |xxxxxxxxxxx00011111000| +----------------------+ 0 32 64 Notice that, we can only do it if the MB is larger than 32 and MB <= ME as RLWINM will replace the content of [0 - 32) with [32 - 64) even we didn't rotate it. Differential Revision: https://reviews.llvm.org/D71829
* [PowerPC] Change default for unaligned FP access for older subtargetsNemanja Ivanovic2019-12-282-1/+45
| | | | | | | | | | | This is a fix for https://bugs.llvm.org/show_bug.cgi?id=40554 Some CPU's trap to the kernel on unaligned floating point access and there are kernels that do not handle the interrupt. The program then fails with a SIGBUS according to the PR. This just switches the default for unaligned access to only allow it on recent server CPUs that are known to allow this. Differential revision: https://reviews.llvm.org/D71954
* [PowerPC] Modify the hasSideEffects of some VSX instructions from 1 to 0Kang Zhang2019-12-281-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen` will set it as true for those instructions which has no match pattern. Below 6 instructions don't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by llvm-tblgen. But in fact below instructions don't modify any special register and don't have other SideEffects, they shouldn't have SideEffects. This patch is to modify the hasSideEffects of below instructions from 1 to 0. ``` VEXTUHLX VEXTUHRX VEXTUWLX VEXTUWRX VSPLTBs VSPLTHs ``` Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D71391
* [PowerPC] stop folding if result rlwinm mask is wrap while original rlwinm ↵czhengsz2019-12-251-0/+15
| | | | | | | | | | | | | | | | | is not. %1:g8rc = RLWINM8 %0:g8rc, 0, 16, 9 %2:g8rc = RLWINM8 killed %1:g8rc, 0, 0, 31 -> %2:g8rc = RLWINM8 %0:g8rc, 0, 16, 9 The above folding is wrong. Before transformation, %2:g8rc is 32 bit value. After transformation, %2:g8rc becomes a 64 bit value. This patch fixes above issue. Reviewed by: steven.zhang Differential Revision: https://reviews.llvm.org/D71833
* [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0Kang Zhang2019-12-2613-52/+52
| | | | | | | | | | | | | | | | | Summary: If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen` will set it as true for those instructions which has no match pattern. The instructions `MTLR` and `MFLR` don't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by `llvm-tblgen`. But in fact, we can use `[LR]` to model the two instructions, so they should not have SideEffects. This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D71390
* Migrate function attribute "no-frame-pointer-elim"="false" to ↵Fangrui Song2019-12-2414-25/+25
| | | | "frame-pointer"="none" as cleanups after D56351
* Migrate function attribute "no-frame-pointer-elim-non-leaf" to ↵Fangrui Song2019-12-247-8/+8
| | | | "frame-pointer"="non-leaf" as cleanups after D56351
* Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" ↵Fangrui Song2019-12-2428-36/+36
| | | | as cleanups after D56351
* [PowerPC] NFC - fix the testcase bug of folding rlwinmczhengsz2019-12-231-7/+7
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* [Power9] Remove the PPCISD::XXREVERSE as it has completely the same ↵QingShan Zhang2019-12-231-3/+2
| | | | | | | | | semantics of ISD::BSWAP The custom node PPCISD::XXREVERSE has completely the same semantics of generic node ISD::BSWAP. We need to clean up it as we have the combine rules for bswap in the base class, while nothing for xxreverse. Differential Revision: https://reviews.llvm.org/D70657
* [NFC][Test][PowerPC] Add more tests for 'and mask'QingShan Zhang2019-12-232-22/+91
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