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| author | Kai Luo <lkail@cn.ibm.com> | 2020-04-01 02:15:25 +0000 |
|---|---|---|
| committer | Tom Stellard <tstellar@redhat.com> | 2020-04-22 14:54:22 -0700 |
| commit | b11ecd196540d87cb7db190d405056984740d2ce (patch) | |
| tree | 20ba8c440d36363f2fccffc7510736a4fffc3ebe /llvm/test/CodeGen/PowerPC | |
| parent | 66cfbf17a18513de5551d6cdda563a2864d13400 (diff) | |
| download | bcm5719-llvm-b11ecd196540d87cb7db190d405056984740d2ce.tar.gz bcm5719-llvm-b11ecd196540d87cb7db190d405056984740d2ce.zip | |
[PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled
Summary:
In https://bugs.llvm.org/show_bug.cgi?id=45297, it fails selecting
instructions for `PPCISD::ST_VSR_SCAL_INT`. The reason it generate the
`PPCISD::ST_VSR_SCAL_INT` with `-power8-vector` in IR is PPC's
combiner checks `hasP8Altivec` rather than `hasP8Vector`. This patch
should resolve PR45297.
Differential Revision: https://reviews.llvm.org/D76773
(cherry picked from commit 8eb40e41f6ec99985a292e342ec303a0bd6f5f41)
Diffstat (limited to 'llvm/test/CodeGen/PowerPC')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/pr45297.ll | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/PowerPC/pr45297.ll b/llvm/test/CodeGen/PowerPC/pr45297.ll index 5bd5df54395..39583d5a04c 100644 --- a/llvm/test/CodeGen/PowerPC/pr45297.ll +++ b/llvm/test/CodeGen/PowerPC/pr45297.ll @@ -1,11 +1,20 @@ -; RUN: not --crash llc -verify-machineinstrs \ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \ ; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec \ ; RUN: -mattr=-power8-vector -mattr=-vsx < %s 2>&1 | FileCheck %s -; CHECK: LLVM ERROR: Cannot select: {{.*}}: ch = PPCISD::ST_VSR_SCAL_INT<(store 4 into @Global)> @Global = dso_local global i32 55, align 4 define dso_local void @test(float %0) local_unnamed_addr { +; CHECK-LABEL: test: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fctiwz f0, f1 +; CHECK-NEXT: addi r3, r1, -4 +; CHECK-NEXT: addis r4, r2, Global@toc@ha +; CHECK-NEXT: stfiwx f0, 0, r3 +; CHECK-NEXT: lwz r3, -4(r1) +; CHECK-NEXT: stw r3, Global@toc@l(r4) +; CHECK-NEXT: blr entry: %1 = fptosi float %0 to i32 store i32 %1, i32* @Global, align 4 |
