| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0 | Kang Zhang | 2019-12-26 | 1 | -3/+3 |
| | | | | | | | | | | | | | | | | | | Summary: If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen` will set it as true for those instructions which has no match pattern. The instructions `MTLR` and `MFLR` don't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by `llvm-tblgen`. But in fact, we can use `[LR]` to model the two instructions, so they should not have SideEffects. This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0. Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D71390 | ||||
| * | [NFC][PowerPC] Consolidate testing of common linkage symbols | Jinsong Ji | 2019-09-20 | 1 | -1/+1 |
| | | | | | | | | Add a new file to test the code gen for common linkage symbol. Remove common linkage in some other testcases to avoid distraction. llvm-svn: 372426 | ||||
| * | [NFC][Regalloc] Add testcases for D66576 | Zi Xuan Wu | 2019-08-26 | 1 | -0/+263 |
| llvm-svn: 369877 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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