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| author | Kang Zhang <shkzhang@cn.ibm.com> | 2019-12-26 02:12:32 +0000 |
|---|---|---|
| committer | Kang Zhang <shkzhang@cn.ibm.com> | 2019-12-26 02:12:32 +0000 |
| commit | 6d88b7d6e712789115c149c5abb0f359d1222545 (patch) | |
| tree | d98ef508266356c4ef90716b3f05a24b1ef5eb0d /llvm/test/CodeGen/PowerPC/csr-split.ll | |
| parent | 6cf6f7dc96d55af63a15fb73499bf81d00f969b3 (diff) | |
| download | bcm5719-llvm-6d88b7d6e712789115c149c5abb0f359d1222545.tar.gz bcm5719-llvm-6d88b7d6e712789115c149c5abb0f359d1222545.zip | |
[PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0
Summary:
If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen`
will set it as true for those instructions which has no match pattern.
The instructions `MTLR` and `MFLR` don't set the hasSideEffects flag and don't
have match pattern, so their hasSideEffects flag will be set true by
`llvm-tblgen`.
But in fact, we can use `[LR]` to model the two instructions, so they should not
have SideEffects.
This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0.
Reviewed By: jsji
Differential Revision: https://reviews.llvm.org/D71390
Diffstat (limited to 'llvm/test/CodeGen/PowerPC/csr-split.ll')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/csr-split.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/PowerPC/csr-split.ll b/llvm/test/CodeGen/PowerPC/csr-split.ll index cd981a27d2e..0e2cf306e99 100644 --- a/llvm/test/CodeGen/PowerPC/csr-split.ll +++ b/llvm/test/CodeGen/PowerPC/csr-split.ll @@ -34,8 +34,8 @@ define dso_local signext i32 @test1(i32* %b) local_unnamed_addr { ; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: addi r1, r1, 48 ; CHECK-PWR9-NEXT: ld r0, 16(r1) -; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: blr ; ; CHECK-LABEL: test1: @@ -116,8 +116,8 @@ define dso_local signext i32 @test2(i32* %p1) local_unnamed_addr { ; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: addi r1, r1, 48 ; CHECK-PWR9-NEXT: ld r0, 16(r1) -; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: blr ; ; CHECK-LABEL: test2: @@ -199,9 +199,9 @@ define dso_local i8* @test3(i8** nocapture %p1, i8 zeroext %p2) local_unnamed_ad ; CHECK-PWR9-NEXT: mr r3, r30 ; CHECK-PWR9-NEXT: addi r1, r1, 64 ; CHECK-PWR9-NEXT: ld r0, 16(r1) -; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload +; CHECK-PWR9-NEXT: mtlr r0 ; CHECK-PWR9-NEXT: blr ; ; CHECK-LABEL: test3: |
