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path: root/llvm/test/CodeGen/MIR/AMDGPU
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* llc: Change behavior of -mcpu with existing attributeMatt Arsenault2020-01-071-2/+5
* llc/MIR: Fix setFunctionAttributes for MIR functionsMatt Arsenault2020-01-062-0/+78
* [llvm][MIRVRegNamerUtils] Adding hashing on memoperands.Puyan Lotfi2019-12-111-0/+42
* [MIRNamer]: Make the check lines in the test robust with regex.Aditya Nandakumar2019-11-161-13/+12
* [MirNamer][Canonicalizer]: Perform instruction semantic based renamingAditya Nandakumar2019-11-151-8/+16
* AMDGPU: Add default denormal mode to MachineFunctionInfoMatt Arsenault2019-11-012-0/+27
* [Alignment] Migrate Attribute::getWith(Stack)AlignmentGuillaume Chatelet2019-10-152-6/+9
* [AMDGPU] Extend buffer intrinsics with swizzlingPiotr Sobczak2019-10-026-22/+22
* [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir...Guillaume Chatelet2019-09-111-1/+1
* AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serializationMatt Arsenault2019-08-272-1/+16
* AMDGPU/LoadStoreOptimizer: combine MMOs when merging instructionsTom Stellard2019-07-291-2/+2
* AMDGPU: Serialize mode from MachineFunctionInfoMatt Arsenault2019-07-102-0/+69
* AMDGPU: Make s34 the FP registerMatt Arsenault2019-07-081-2/+2
* [AMDGPU] Enable serializing of argument info.Michael Liao2019-07-032-0/+80
* AMDGPU: Write LDS objects out as global symbols in code generationNicolai Haehnle2019-06-251-1/+1
* AMDGPU: Always use s33 for global scratch wave offsetMatt Arsenault2019-06-201-2/+2
* Rename ExpandISelPseudo->FinalizeISel, delay register reservationMatt Arsenault2019-06-191-1/+1
* Describe stack-id as an enumSander de Smalen2019-06-171-10/+10
* AMDGPU: Prepare for explicit absolute relocations in code generationNicolai Haehnle2019-06-161-1/+3
* AMDGPU: Invert frame index offset interpretationMatt Arsenault2019-06-051-2/+2
* [MIR-Canon] Don't do vreg skip for independent instructions if there are none.Puyan Lotfi2019-05-311-0/+1
* [MIR-Canon] Hardening propagateLocalCopies.Puyan Lotfi2019-05-311-2/+7
* [AMDGPU] gfx1010 tests. NFC.Stanislav Mekhanoshin2019-05-131-0/+155
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-304-25/+25
* AMDGPU: Don't use the default cpu in a few testsMatt Arsenault2019-04-031-1/+1
* MIR: Freeze reserved regs after parsing everythingMatt Arsenault2019-03-271-0/+29
* MIR: Allow targets to serialize MachineFunctionInfoMatt Arsenault2019-03-1412-0/+358
* [AMDGPU] Add support for immediate operand for S_ENDPGMDavid Stuttard2019-03-127-9/+9
* AMDGPU: Fix tests using old number for constant address spaceMatt Arsenault2018-09-104-29/+29
* [MIR-Canon] Fixing a test failure caused by COPY Folding.Puyan Lotfi2018-04-161-3/+1
* Attempting to work around a non-determinism issue.Puyan Lotfi2018-04-111-2/+0
* [MIR-Canon] Improving performance by switching to named vregs.Puyan Lotfi2018-04-051-6/+6
* [MIR-Canon] Adding support for multi-def -> user distance reduction.Puyan Lotfi2018-04-051-0/+32
* [GISel]: Verify COPIES involving generic registers.Aditya Nandakumar2018-02-091-2/+2
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-315-105/+105
* [MIR] Add support for addrspace in MIRFrancis Visoiu Mistrih2018-01-261-3/+3
* Move tests to the correct placeMatthias Braun2018-01-196-1356/+0
* [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.Puyan Lotfi2018-01-103-6/+6
* MIR: Print the register class or bank in vreg defsJustin Bogner2017-10-244-31/+31
* Canonicalize a large number of mir tests using update_mir_test_checksJustin Bogner2017-10-182-3/+8
* AMDGPU: Handle non-temporal loads and storesKonstantin Zhuravlyov2017-09-073-9/+333
* AMDGPU: Handle more than one memory operand in SIMemoryLegalizerKonstantin Zhuravlyov2017-09-071-0/+163
* AMDGPU: Implement memory modelKonstantin Zhuravlyov2017-07-211-0/+122
* Add an ID field to StackObjectsMatt Arsenault2017-07-201-0/+35
* AMDGPU: Fix crash when folding immediates into multiple usesNicolai Haehnle2017-07-181-0/+40
* Enhance synchscope representationKonstantin Zhuravlyov2017-07-111-0/+98
* AMDGPU: Allow SIShrinkInstructions to work in non-SSAMatt Arsenault2017-07-101-10/+10
* AMDGPU: Add operand target flags serializationMatt Arsenault2017-07-021-0/+29
* AMDGPU: Remove legacy bfe intrinsicsMatt Arsenault2017-04-031-2/+2
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-215-14/+14
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