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authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-10-27 23:38:52 -0700
committerMatt Arsenault <arsenm2@gmail.com>2019-11-01 00:03:39 -0700
commit19e7f8a21d62d0a6ae8a1bbecb232bd9d520555b (patch)
treea3c2d9fe4c56d8076c20280d5de9328f3803d464 /llvm/test/CodeGen/MIR/AMDGPU
parentcb6822c9deb63b6c21263b3732e549fdc89c4bbf (diff)
downloadbcm5719-llvm-19e7f8a21d62d0a6ae8a1bbecb232bd9d520555b.tar.gz
bcm5719-llvm-19e7f8a21d62d0a6ae8a1bbecb232bd9d520555b.zip
AMDGPU: Add default denormal mode to MachineFunctionInfo
The default FP mode should really be a property of a specific function, and not a subtarget. Introduce the necessary fields to the SIMachineFunctionInfo to help move towards this goal.
Diffstat (limited to 'llvm/test/CodeGen/MIR/AMDGPU')
-rw-r--r--llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir13
-rw-r--r--llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll14
2 files changed, 27 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
index 8334ef5ef6c..0b23ded5d9d 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
@@ -25,6 +25,8 @@
# FULL-NEXT: mode:
# FULL-NEXT: ieee: true
# FULL-NEXT: dx10-clamp: true
+# FULL-NEXT: fp32-denormals: true
+# FULL-NEXT: fp64-fp16-denormals: true
# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: body:
@@ -92,6 +94,8 @@ body: |
# FULL-NEXT: mode:
# FULL-NEXT: ieee: true
# FULL-NEXT: dx10-clamp: true
+# FULL-NEXT: fp32-denormals: true
+# FULL-NEXT: fp64-fp16-denormals: true
# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: body:
@@ -129,6 +133,8 @@ body: |
# FULL-NEXT: mode:
# FULL-NEXT: ieee: true
# FULL-NEXT: dx10-clamp: true
+# FULL-NEXT: fp32-denormals: true
+# FULL-NEXT: fp64-fp16-denormals: true
# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: body:
@@ -167,6 +173,8 @@ body: |
# FULL-NEXT: mode:
# FULL-NEXT: ieee: true
# FULL-NEXT: dx10-clamp: true
+# FULL-NEXT: fp32-denormals: true
+# FULL-NEXT: fp64-fp16-denormals: true
# FULL-NEXT: highBitsOf32BitAddress: 0
# FULL-NEXT: body:
@@ -239,11 +247,16 @@ body: |
# ALL: mode:
# ALL-NEXT: ieee: false
# ALL-NEXT: dx10-clamp: false
+# ALL-NEXT: fp32-denormals: false
+# ALL-NEXT: fp64-fp16-denormals: false
+
name: parse_mode
machineFunctionInfo:
mode:
ieee: false
dx10-clamp: false
+ fp32-denormals: false
+ fp64-fp16-denormals: false
body: |
bb.0:
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
index bc354f2a0d8..f9de722c567 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info.ll
@@ -28,6 +28,8 @@
; CHECK-NEXT: mode:
; CHECK-NEXT: ieee: true
; CHECK-NEXT: dx10-clamp: true
+; CHECK-NEXT: fp32-denormals: false
+; CHECK-NEXT: fp64-fp16-denormals: true
; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: body:
define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
@@ -55,6 +57,8 @@ define amdgpu_kernel void @kernel(i32 %arg0, i64 %arg1, <16 x i32> %arg2) {
; CHECK-NEXT: mode:
; CHECK-NEXT: ieee: false
; CHECK-NEXT: dx10-clamp: true
+; CHECK-NEXT: fp32-denormals: false
+; CHECK-NEXT: fp64-fp16-denormals: true
; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: body:
define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
@@ -80,6 +84,8 @@ define amdgpu_ps void @ps_shader(i32 %arg0, i32 inreg %arg1) {
; CHECK-NEXT: mode:
; CHECK-NEXT: ieee: true
; CHECK-NEXT: dx10-clamp: true
+; CHECK-NEXT: fp32-denormals: false
+; CHECK-NEXT: fp64-fp16-denormals: true
; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: body:
define void @function() {
@@ -105,6 +111,8 @@ define void @function() {
; CHECK-NEXT: mode:
; CHECK-NEXT: ieee: true
; CHECK-NEXT: dx10-clamp: true
+; CHECK-NEXT: fp32-denormals: false
+; CHECK-NEXT: fp64-fp16-denormals: true
; CHECK-NEXT: highBitsOf32BitAddress: 0
; CHECK-NEXT: body:
define void @function_nsz() #0 {
@@ -115,6 +123,8 @@ define void @function_nsz() #0 {
; CHECK: mode:
; CHECK-NEXT: ieee: true
; CHECK-NEXT: dx10-clamp: false
+; CHECK-NEXT: fp32-denormals: false
+; CHECK-NEXT: fp64-fp16-denormals: true
define void @function_dx10_clamp_off() #1 {
ret void
}
@@ -123,6 +133,8 @@ define void @function_dx10_clamp_off() #1 {
; CHECK: mode:
; CHECK-NEXT: ieee: false
; CHECK-NEXT: dx10-clamp: true
+; CHECK-NEXT: fp32-denormals: false
+; CHECK-NEXT: fp64-fp16-denormals: true
define void @function_ieee_off() #2 {
ret void
}
@@ -131,6 +143,8 @@ define void @function_ieee_off() #2 {
; CHECK: mode:
; CHECK-NEXT: ieee: false
; CHECK-NEXT: dx10-clamp: false
+; CHECK-NEXT: fp32-denormals: false
+; CHECK-NEXT: fp64-fp16-denormals: true
define void @function_ieee_off_dx10_clamp_off() #3 {
ret void
}
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