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* Fix CellSPU vector shuffles, again.Kalle Raiskila2010-09-081-0/+26
| | | | | | Some cases of lowering to rotate were miscompiled. llvm-svn: 113355
* Fix lowering of INSERT_VECTOR_ELT in SPU. Kalle Raiskila2010-08-291-0/+8
| | | | | | The IDX was treated as byte index, not element index. llvm-svn: 112422
* Fix SPU BE to use all the available return registers.Kalle Raiskila2010-08-241-2/+24
| | | | | | llc used to assert on the added testcase. llvm-svn: 111911
* Fix a bug with insertelement on SPU. Kalle Raiskila2010-08-181-0/+15
| | | | | | | The previous algorithm in LowerVECTOR_SHUFFLE didn't check all requirements for "monotonic" shuffles. llvm-svn: 111361
* Remove all traces of v2[i,f]32 on SPU. Kalle Raiskila2010-08-183-10/+10
| | | | | | | | The "half vectors" are now widened to full size by the legalizer. The only exception is in parameter passing, where half vectors are expanded. This causes changes to some dejagnu tests. llvm-svn: 111360
* Change SPU C calling convention to match that described in Kalle Raiskila2010-08-181-0/+33
| | | | | | | | "SPU Application Binary Interface Specification, v1.9" by IBM. Specifically: use r3-r74 to pass parameters and the return value. llvm-svn: 111358
* Have SPU handle halfvec stores aligned by 8 bytes.Kalle Raiskila2010-08-092-3/+15
| | | | llvm-svn: 110576
* Make SPU backend handle insertelement and Kalle Raiskila2010-08-042-0/+25
| | | | | | store for "half vectors" llvm-svn: 110198
* More SPU v2f32 stuff added: insertelement and shuffle.Kalle Raiskila2010-08-021-0/+10
| | | | llvm-svn: 110038
* Add preliminary v2f32 support for SPU. Like with v2i32, we justKalle Raiskila2010-08-021-0/+35
| | | | | | | | duplicate the instructions and operate on half vectors. Also reorder code in SPUInstrInfo.td for better coherency. llvm-svn: 110037
* Add preliminary v2i32 support for SPU backend. As there are noKalle Raiskila2010-08-021-0/+57
| | | | | | | | | | such registers in SPU, this support boils down to "emulating" them by duplicating instructions on the general purpose registers. This adds the most basic operations on v2i32: passing parameters, addition, subtraction, multiplication and a few others. llvm-svn: 110035
* Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.Jakob Stoklund Olesen2010-07-161-1/+1
| | | | | | TII::isMoveInstr is going tobe completely removed. llvm-svn: 108507
* Fix some tests that didn't test anything.Benjamin Kramer2010-06-261-1/+1
| | | | llvm-svn: 106954
* Add the check to the testcase of r106419.Kalle Raiskila2010-06-211-0/+3
| | | | llvm-svn: 106421
* Mark the SPU 'lr' instruction to never have side effects. Kalle Raiskila2010-06-214-13/+18
| | | | | | | | | This allows the fast regiser allocator to remove redundant register moves. Update a set of tests that depend on the register allocator to be linear scan. llvm-svn: 106420
* Fix the lowering of VECTOR_SHUFFLE on SPU to handle splats.Kalle Raiskila2010-06-211-1/+6
| | | | llvm-svn: 106419
* Fix lowering of VECTOR_SHUFFLE on SPU. Old algorithmKalle Raiskila2010-06-211-0/+10
| | | | | | | used to choke llc with the attached test. llvm-svn: 106411
* Fix SPU to cope with vector insertelement to an undef position.Kalle Raiskila2010-06-091-2/+13
| | | | | | We default to inserting to lane 0. llvm-svn: 105722
* Handle loading from/storing to undef pointers on SPU by inserting a Kalle Raiskila2010-06-091-0/+5
| | | | | | random load/store, rather than crashing llc. llvm-svn: 105710
* Fix handling of 'load' nodes.Kalle Raiskila2010-06-011-0/+13
| | | | llvm-svn: 105269
* Make SPU backend not assert on jump tables.Kalle Raiskila2010-05-111-0/+21
| | | | llvm-svn: 103466
* Fix encoding of 'sf' and 'sfh' instructions.Kalle Raiskila2010-05-101-0/+26
| | | | llvm-svn: 103399
* "on the rare occasion the SPU BE produces illegal assembly - it tries to ↵Chris Lattner2010-05-041-0/+13
| | | | | | | | emit an add instruction of the form 'a reg, reg, imm'." Patch by Kalle Raiskila! llvm-svn: 103021
* teach cellspu how to return i8 and i16 from calls,Chris Lattner2010-04-201-0/+8
| | | | | | patch by Kalle Raiskila! llvm-svn: 101875
* Make sure this test tests something.Benjamin Kramer2010-04-091-3/+7
| | | | llvm-svn: 100879
* "On SPU, variables in the .bss section that are allocated with the .lcomm ↵Chris Lattner2010-04-091-0/+2
| | | | | | | | | | directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment. this patch disables .lcomm in favour of '.local .comm' Patch by Kalle Raisklia! llvm-svn: 100875
* Split big test into multiple directories to cater toDale Johannesen2010-04-071-0/+33
| | | | | | those who don't build all targets. llvm-svn: 100688
* From Kalle Raiskila:Chris Lattner2010-03-291-0/+17
| | | | | | | | "the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions: -in vararg handling, registers are marked to be live, to not confuse the register scavenger -function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack." llvm-svn: 99819
* fix bss section printing for cell, patch by Kalle Raiskila!Chris Lattner2010-03-051-0/+5
| | | | llvm-svn: 97814
* don't let asm-verbose break the check-next lines in these tests.Chris Lattner2010-01-191-2/+2
| | | | llvm-svn: 93869
* Teach dag combine to fold the following transformation more aggressively:Evan Cheng2010-01-061-1/+0
| | | | | | | | | | (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel. This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places. llvm-svn: 92849
* Delete useless trailing semicolons.Dan Gohman2010-01-052-2/+2
| | | | llvm-svn: 92740
* Revert this dag combine change:Evan Cheng2009-12-171-4/+4
| | | | | | | | Fold (zext (and x, cst)) -> (and (zext x), cst) DAG combiner likes to optimize expression in the other way so this would end up cause an infinite looping. llvm-svn: 91574
* Fold (zext (and x, cst)) -> (and (zext x), cst).Evan Cheng2009-12-151-4/+4
| | | | llvm-svn: 91380
* Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 ↵Evan Cheng2009-12-091-3/+3
| | | | | | isl lowering code. llvm-svn: 90925
* Revert the main portion of r31856. It was causing BranchFoldingDan Gohman2009-10-221-1/+1
| | | | | | | | | | | | to break up CFG diamonds by banishing one of the blocks to the end of the function, which is bad for code density and branch size. This does pessimize MultiSource/Benchmarks/Ptrdist/yacr2, the benchmark cited as the reason for the change, however I've examined the code and it looks more like a case of gaming a particular branch than of being generally applicable. llvm-svn: 84803
* Teach lit that the .c files in 'test/CodeGen/CellSPU/useful-harnesses' ↵Daniel Dunbar2009-10-191-0/+1
| | | | | | aren't tests. llvm-svn: 84460
* Convert more tests to avoid llvm-as.Dan Gohman2009-09-1138-41/+41
| | | | llvm-svn: 81545
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-093-3/+3
| | | | llvm-svn: 81293
* Updated i128 sext support for CellSPU backend, contributed by Ken Werner (IBM)Scott Michel2009-08-251-3/+32
| | | | llvm-svn: 80042
* Remove obsolete -f flags.Dan Gohman2009-08-251-1/+1
| | | | llvm-svn: 79992
* - Remove SelectSEXTi128 from SPUISelDAGToDAG.cpp, evidently, this is redundantScott Michel2009-08-241-5/+5
| | | | | | | | code, according to Anton (I'm not totally convinced, but we can always resurrect patches if we need to do so.) - Start moving CellSPU's tests to prefer FileCheck. llvm-svn: 79958
* Prefer 'FileCheck' over 'grep'.Scott Michel2009-08-241-7/+8
| | | | llvm-svn: 79953
* 128-bit sign extension and vector shift cleanups, contributed by Ken WernerScott Michel2009-08-241-0/+17
| | | | | | (IBM). llvm-svn: 79949
* Add some generic expansion logic for SMULO and UMULO. Fixes UMULO Eli Friedman2009-06-161-0/+15
| | | | | | | | support for x86, and UMULO/SMULO for many architectures, including PPC (PR4201), ARM, and Cell. The resulting expansion isn't perfect, but it's not bad. llvm-svn: 73477
* Split the Add, Sub, and Mul instruction opcodes into separateDan Gohman2009-06-043-50/+50
| | | | | | | | | | | | | | | integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
* Revert 67132. This is breaking some objective-c apps.Evan Cheng2009-03-257-8/+20
| | | | | | Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext. llvm-svn: 67701
* Don't force promotion of return arguments on the callee.Rafael Espindola2009-03-179-22/+10
| | | | | | | Some architectures (like x86) don't require it. This fixes bug 3779. llvm-svn: 67132
* CellSPU:Scott Michel2009-03-171-1/+1
| | | | | | Revert inadvertent mis-fix of fneg. llvm-svn: 67084
* CellSPU:Scott Michel2009-03-172-9/+7
| | | | | | | | | | | | - Fix fabs, fneg for f32 and f64. - Use BuildVectorSDNode.isConstantSplat, now that the functionality exists - Continue to improve i64 constant lowering. Lower certain special constants to the constant pool when they correspond to SPU's shufb instruction's special mask values. This avoids the overhead of performing a shuffle on a zero-filled vector just to get the special constant when the memory load suffices. llvm-svn: 67067
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