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| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-09-08 11:53:38 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-09-08 11:53:38 +0000 |
| commit | e542972828ce89018a6bf3fbb06a9dc91815b243 (patch) | |
| tree | 9aafbe052149976a0c0320e6ba202a93c7220eb6 /llvm/test/CodeGen/CellSPU | |
| parent | 4ad4b58639472b729d8b67b7315abf8f258fa315 (diff) | |
| download | bcm5719-llvm-e542972828ce89018a6bf3fbb06a9dc91815b243.tar.gz bcm5719-llvm-e542972828ce89018a6bf3fbb06a9dc91815b243.zip | |
Fix CellSPU vector shuffles, again.
Some cases of lowering to rotate were miscompiled.
llvm-svn: 113355
Diffstat (limited to 'llvm/test/CodeGen/CellSPU')
| -rw-r--r-- | llvm/test/CodeGen/CellSPU/shuffles.ll | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/CellSPU/shuffles.ll b/llvm/test/CodeGen/CellSPU/shuffles.ll index f37d2ae89b0..94b5fbd6baa 100644 --- a/llvm/test/CodeGen/CellSPU/shuffles.ll +++ b/llvm/test/CodeGen/CellSPU/shuffles.ll @@ -39,3 +39,29 @@ define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) { ret <4 x float> %rv } +define <2 x i32> @test_v2i32(<4 x i32>%vec) +{ +;CHECK: rotqbyi $3, $3, 4 +;CHECK: bi $lr + %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, <2 x i32><i32 1,i32 2> + ret <2 x i32> %rv +} + +define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec) +{ +;CHECK: rotqbyi $3, $3, 8 +;CHECK: bi $lr + %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, + <4 x i32> <i32 2,i32 3,i32 0, i32 1> + ret <4 x i32> %rv +} + +define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec) +{ +;CHECK: rotqbyi $3, $3, 4 +;CHECK: bi $lr + %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, + <4 x i32> <i32 1,i32 2,i32 3, i32 0> + ret <4 x i32> %rv +} + |
