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| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-06-09 09:58:17 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-06-09 09:58:17 +0000 |
| commit | 5e0862f7f567ec6a620422299c5a8ce02b94ce3f (patch) | |
| tree | 4c6cd55f27cef89056fe1eda43a5424a4b7c66d6 /llvm/test/CodeGen/CellSPU | |
| parent | 53444d394fd4b95b9465c4517b3714bb0ce3e0ce (diff) | |
| download | bcm5719-llvm-5e0862f7f567ec6a620422299c5a8ce02b94ce3f.tar.gz bcm5719-llvm-5e0862f7f567ec6a620422299c5a8ce02b94ce3f.zip | |
Fix SPU to cope with vector insertelement to an undef position.
We default to inserting to lane 0.
llvm-svn: 105722
Diffstat (limited to 'llvm/test/CodeGen/CellSPU')
| -rw-r--r-- | llvm/test/CodeGen/CellSPU/vecinsert.ll | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/CellSPU/vecinsert.ll b/llvm/test/CodeGen/CellSPU/vecinsert.ll index 9a00c1f29f8..8dcab1d84c9 100644 --- a/llvm/test/CodeGen/CellSPU/vecinsert.ll +++ b/llvm/test/CodeGen/CellSPU/vecinsert.ll @@ -1,17 +1,19 @@ ; RUN: llc < %s -march=cellspu > %t1.s ; RUN: grep cbd %t1.s | count 5 ; RUN: grep chd %t1.s | count 5 -; RUN: grep cwd %t1.s | count 10 +; RUN: grep cwd %t1.s | count 11 ; RUN: grep -w il %t1.s | count 5 ; RUN: grep -w ilh %t1.s | count 6 ; RUN: grep iohl %t1.s | count 1 ; RUN: grep ilhu %t1.s | count 4 -; RUN: grep shufb %t1.s | count 26 +; RUN: grep shufb %t1.s | count 27 ; RUN: grep 17219 %t1.s | count 1 ; RUN: grep 22598 %t1.s | count 1 ; RUN: grep -- -39 %t1.s | count 1 ; RUN: grep 24 %t1.s | count 1 ; RUN: grep 1159 %t1.s | count 1 +; RUN: FileCheck %s < %t1.s + ; ModuleID = 'vecinsert.bc' target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128" target triple = "spu-unknown-elf" @@ -118,3 +120,12 @@ entry: store <2 x double> %tmp3, <2 x double>* %arrayidx ret void } + +define <4 x i32> @undef_v4i32( i32 %param ) { + ;CHECK: cwd + ;CHECK: lqa + ;CHECK: shufb + %val = insertelement <4 x i32> <i32 1, i32 2, i32 3, i32 4>, i32 %param, i32 undef + ret <4 x i32> %val +} + |
