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authorEvan Cheng <evan.cheng@apple.com>2009-12-09 01:53:58 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-12-09 01:53:58 +0000
commitd938faff4b27248e0c2eac9858562ba778097ea6 (patch)
tree850f39c63df45e2eb6642db7e87425696ac18c99 /llvm/test/CodeGen/CellSPU
parent85d9968533265d159ff34802170712cccebca1c9 (diff)
downloadbcm5719-llvm-d938faff4b27248e0c2eac9858562ba778097ea6.tar.gz
bcm5719-llvm-d938faff4b27248e0c2eac9858562ba778097ea6.zip
Teach InferPtrAlignment to infer GV+cst alignment and use it to simplify x86 isl lowering code.
llvm-svn: 90925
Diffstat (limited to 'llvm/test/CodeGen/CellSPU')
-rw-r--r--llvm/test/CodeGen/CellSPU/call_indirect.ll6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/CellSPU/call_indirect.ll b/llvm/test/CodeGen/CellSPU/call_indirect.ll
index 639c794424f..f25d6b5810f 100644
--- a/llvm/test/CodeGen/CellSPU/call_indirect.ll
+++ b/llvm/test/CodeGen/CellSPU/call_indirect.ll
@@ -2,17 +2,17 @@
; RUN: llc < %s -march=cellspu -mattr=large_mem > %t2.s
; RUN: grep bisl %t1.s | count 7
; RUN: grep ila %t1.s | count 1
-; RUN: grep rotqby %t1.s | count 6
+; RUN: grep rotqby %t1.s | count 5
; RUN: grep lqa %t1.s | count 1
; RUN: grep lqd %t1.s | count 12
; RUN: grep dispatch_tab %t1.s | count 5
; RUN: grep bisl %t2.s | count 7
; RUN: grep ilhu %t2.s | count 2
; RUN: grep iohl %t2.s | count 2
-; RUN: grep rotqby %t2.s | count 6
+; RUN: grep rotqby %t2.s | count 5
; RUN: grep lqd %t2.s | count 13
; RUN: grep ilhu %t2.s | count 2
-; RUN: grep ai %t2.s | count 9
+; RUN: grep ai %t2.s | count 8
; RUN: grep dispatch_tab %t2.s | count 6
; ModuleID = 'call_indirect.bc'
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