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| author | Scott Michel <scottm@aero.org> | 2009-03-17 01:15:45 +0000 |
|---|---|---|
| committer | Scott Michel <scottm@aero.org> | 2009-03-17 01:15:45 +0000 |
| commit | 839ad0a5f37ab3653b25724d6aca0309b928818d (patch) | |
| tree | 2fec919f697dd794cd635885fc765877b2a93dd2 /llvm/test/CodeGen/CellSPU | |
| parent | 2d603dae2cd8cff21514921dc228279091be404b (diff) | |
| download | bcm5719-llvm-839ad0a5f37ab3653b25724d6aca0309b928818d.tar.gz bcm5719-llvm-839ad0a5f37ab3653b25724d6aca0309b928818d.zip | |
CellSPU:
- Fix fabs, fneg for f32 and f64.
- Use BuildVectorSDNode.isConstantSplat, now that the functionality exists
- Continue to improve i64 constant lowering. Lower certain special constants
to the constant pool when they correspond to SPU's shufb instruction's
special mask values. This avoids the overhead of performing a shuffle on a
zero-filled vector just to get the special constant when the memory load
suffices.
llvm-svn: 67067
Diffstat (limited to 'llvm/test/CodeGen/CellSPU')
| -rw-r--r-- | llvm/test/CodeGen/CellSPU/2009-01-01-BrCond.ll | 10 | ||||
| -rw-r--r-- | llvm/test/CodeGen/CellSPU/fneg-fabs.ll | 6 |
2 files changed, 7 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/CellSPU/2009-01-01-BrCond.ll b/llvm/test/CodeGen/CellSPU/2009-01-01-BrCond.ll index 3002bbc2517..75e0ed0cd2f 100644 --- a/llvm/test/CodeGen/CellSPU/2009-01-01-BrCond.ll +++ b/llvm/test/CodeGen/CellSPU/2009-01-01-BrCond.ll @@ -8,11 +8,11 @@ target triple = "spu" define double @__floatunsidf(i32 %arg_a) nounwind { entry: - %in = alloca %struct.fp_number_type, align 8 ; <%struct.fp_number_type*> [#uses=5] - %0 = getelementptr %struct.fp_number_type* %in, i32 0, i32 1 ; <i32*> [#uses=1] + %in = alloca %struct.fp_number_type, align 16 + %0 = getelementptr %struct.fp_number_type* %in, i32 0, i32 1 store i32 0, i32* %0, align 4 - %1 = icmp eq i32 %arg_a, 0 ; <i1> [#uses=1] - %2 = getelementptr %struct.fp_number_type* %in, i32 0, i32 0 ; <i32*> [#uses=2] + %1 = icmp eq i32 %arg_a, 0 + %2 = getelementptr %struct.fp_number_type* %in, i32 0, i32 0 br i1 %1, label %bb, label %bb1 bb: ; preds = %entry @@ -26,6 +26,6 @@ bb7: ; preds = %bb5, %bb1, %bb ret double 1.0 } -declare i32 @llvm.ctlz.i32(i32) nounwind readnone +; declare i32 @llvm.ctlz.i32(i32) nounwind readnone declare double @__pack_d(%struct.fp_number_type*) diff --git a/llvm/test/CodeGen/CellSPU/fneg-fabs.ll b/llvm/test/CodeGen/CellSPU/fneg-fabs.ll index b6eca10803e..e8374b3dae2 100644 --- a/llvm/test/CodeGen/CellSPU/fneg-fabs.ll +++ b/llvm/test/CodeGen/CellSPU/fneg-fabs.ll @@ -1,9 +1,7 @@ ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s -; RUN: grep fsmbi %t1.s | count 3 ; RUN: grep 32768 %t1.s | count 2 -; RUN: grep xor %t1.s | count 4 -; RUN: grep and %t1.s | count 5 -; RUN: grep andbi %t1.s | count 3 +; RUN: grep or %t1.s | count 4 +; RUN: grep and %t1.s | count 2 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" |
