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path: root/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll
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* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-2/+2
* [CodeGen] Don't print "pred:" and "opt:" in -debug outputFrancis Visoiu Mistrih2018-01-091-2/+2
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-2/+2
* [CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih2017-11-281-2/+2
* [ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]la...Jeroen Ketema2015-09-301-2/+2
* Fix a nasty bug in DAGCombine of STORE nodes.Owen Anderson2015-03-191-1/+1
* [opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie2015-02-271-3/+3
* ARM: fixup more tests to specify the target more explicitlySaleem Abdulrasool2014-04-031-1/+2
* PR 18466: Fix ARM Pseudo ExpansionWeiming Zhao2014-01-151-0/+55
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