diff options
| author | Jeroen Ketema <j.ketema@imperial.ac.uk> | 2015-09-30 10:56:37 +0000 |
|---|---|---|
| committer | Jeroen Ketema <j.ketema@imperial.ac.uk> | 2015-09-30 10:56:37 +0000 |
| commit | ab99b59e8ca28f5366fb95b497e64ae44d67a9ca (patch) | |
| tree | a9b8c1d1af1f1c409aa1e51dcfd9ea96fdf314f1 /llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll | |
| parent | 42e651fa43747743a6161b1c53e59c743d52a71c (diff) | |
| download | bcm5719-llvm-ab99b59e8ca28f5366fb95b497e64ae44d67a9ca.tar.gz bcm5719-llvm-ab99b59e8ca28f5366fb95b497e64ae44d67a9ca.zip | |
[ARM][NEON] Use address space in vld([1234]|[234]lane) and vst([1234]|[234]lane) instructions
This commit changes the interface of the vld[1234], vld[234]lane, and vst[1234],
vst[234]lane ARM neon intrinsics and associates an address space with the
pointer that these intrinsics take. This changes, e.g.,
<2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32)
to
<2 x i32> @llvm.arm.neon.vld1.v2i32.p0i8(i8*, i32)
This change ensures that address spaces are fully taken into account in the ARM
target during lowering of interleaved loads and stores.
Differential Revision: http://reviews.llvm.org/D12985
llvm-svn: 248887
Diffstat (limited to 'llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll b/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll index ef575f4c41e..be87a2fb1c8 100644 --- a/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll +++ b/llvm/test/CodeGen/ARM/2014-01-09-pseudo_expand_implicit_reg.ll @@ -27,7 +27,7 @@ entry: %n0 = insertelement <2 x i64> undef, i64 %tmp0, i32 0 %n1 = insertelement <2 x i64> %n0, i64 %tmp1, i32 1 - call void @llvm.arm.neon.vst4.v1i64(i8* %m, <1 x i64> %s0, <1 x i64> %s1, <1 x i64> %s2, <1 x i64> %s3, i32 8) + call void @llvm.arm.neon.vst4.p0i8.v1i64(i8* %m, <1 x i64> %s0, <1 x i64> %s1, <1 x i64> %s2, <1 x i64> %s3, i32 8) call void @bar(<2 x i64> %n1) @@ -50,7 +50,7 @@ define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C ret <8 x i8> %tmp8 } -declare void @llvm.arm.neon.vst4.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32) +declare void @llvm.arm.neon.vst4.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32) declare <8 x i8> @llvm.arm.neon.vtbx4(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>) nounwind readnone declare void @bar2(%struct.__neon_int8x8x4_t, <8 x i8>) declare void @bar(<2 x i64> %arg) |
